THS6042_16 Datasheet, PDF (23/46 Pages) Texas Instruments – 350mA,12V ADSL CPE LINE DRIVERS

THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G − MARCH 2000 − REVISED DECEMBER 2001
APPLICATION INFORMATION
PCB design considerations (continued)
D Proper power supply decoupling − Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the
supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible
to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor
less effective. The designer should strive for distances of less than 0.1 inches between the device power
terminal and the ceramic capacitors.
D Differential power supply decoupling − The THS6042/3 were designed for driving low-impedance
differential signals. The 50-Ω load which each amplifier drives causes large amounts of currents to flow from
amplifier to amplifier. Power supply decoupling for differential current signals must be accounted for to
ensure low distortion of the THS6042/3. By simply connecting a 0.1-µF to 1-µF ceramic capacitor from the
+V_CC pin to the −V_CC pin, differential current loops will be minimized (see Figure 37). This will help keep
the THS6042/3 operating at peak performance.
Because of its power dissipation, proper thermal management of the THS6042/3 is required. Even though the
THS6042 and THS6043 PowerPADs are different, the general methodology is the same. Although there are
many ways to properly heatsink these devices, the following steps illustrate one recommended approach for
a multilayer PCB with an internal ground plane. Refer to Figure 43 for the following steps.
Thermal pad area (0.15 x 0.17) with 6 vias
(Via diameter = 13 mils)
Figure 43. THS6043 PowerPAD PCB Etch and Via Pattern − Minimum Requirements
1. Place 6 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept small
so that solder wicking through the holes is not a problem during reflow.
2. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This will
help dissipate the heat generated from the THS6042/3. These additional vias may be larger than the 13 mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered, therefore, wicking is generally not a problem.
3. Connect all holes to the internal ground plane.
4. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS6042/3 package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated through hole.
5. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with
its 6 holes. The bottom-side solder mask should cover the 6 holes of the thermal pad area. This eliminates
the solder from being pulled away from the thermal pad area during the reflow process.
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