DDC118_16 Datasheet, PDF (23/36 Pages) Texas Instruments – Octal Current Input, 20-Bit Analog-To-Digital Converter

DDC118
www.ti.com
RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)
Date retrieval before CONV toggles is the most
straightforward method. Data retrieval begins soon after
DVALID goes low and finishes before CONV toggles, as
shown in Figure 23. For best performance, data retrieval
must stop t₂₈ before CONV toggles. This method is most
appropriate for longer integration times. The maximum
time available for readback is T_INT – t₂₇ – t₂₈. For DCLK =
10MHz and CLK = 4MHz, the maximum number of
DDC118s that can be daisy-chained together (FORMAT =
high) is calculated by Equation 1:
T_INT * 355.125ms
160t_DCLK
(1)
SBAS325B − JUNE 2004 − REVISED APRIL 2009
NOTE: 128τ_DCLK is used for FORMAT = low.
where τ_DCLK is the period of the data clock. For example,
if T_INT = 1000µs and DCLK = 10MHz, the maximum
number of DDC118s (FORMAT = high) is shown in
Equation 2:
1000ms * 355.125ms
(160)(100ns)
+
40.30
³
40DDC118s
(2)
(or 50 for FORMAT = low).
CONV
DVALID
DCLK
DOUT
T_INT
t₂₇
t₂₈
…
…
Side B
Data
T_INT
…
…
Side A
Data
SYMBOL DESCRIPTION
t27
Cont Mode Data Ready
t28
Data Retrieval Shutdown Before Edge of CONV
CLK = 4MHz, CLK_4X = 0
MIN
TYP
MAX
345.00 ± 0.125
10
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
MAX
287.5 ± 0.104
10
UNITS
µs
µs
Figure 23. Readback Before CONV Toggles
23