DDC118_16 Datasheet, PDF (11/36 Pages) Texas Instruments – Octal Current Input, 20-Bit Analog-To-Digital Converter

DDC118
www.ti.com
At the completion of an A/D conversion, the charge on the
integration capacitor (C_F) is reset with S_REF1 and S_RESET
(see Figure 4 and Figure 5a). In this manner, the selected
capacitor is charged to the reference voltage, VREF. Once
the integration capacitor is charged, S_REF1 and S_RESET
are switched so that VREF is no longer connected to the
amplifier circuit while it waits to begin integrating (see
Figure 5b). With the rising edge of CONV, S_INTA closes,
which begins the integration of side A. This process puts
the integrator stage into its integrate mode (see Figure 5c).
Charge from the input signal is collected on the integration
capacitor, causing the voltage output of the amplifier to
decrease. The falling edge of CONV stops the integration
by switching the input signal from side A to side B (S_INTA
and S_INTB). Prior to the falling edge of CONV, the signal on
side B was converted by the A/D converter and reset
during the time that side A was integrating. With the falling
edge of CONV, side B starts integrating the input signal.
Now the output voltage of the side A operational amplifier
is presented to the input of the ∆Σ A/D converter (see
Figure 5d).
Integration Capacitors
There are eight different capacitors available on-chip for
both sides of every channel in the DDC118. These internal
capacitors are trimmed in production to achieve the
specified performance for range error of the DDC118. The
range control pins (RANGE0-RANGE2) change the
capacitor value for all four integrators. Consequently, all
inputs and both sides of each input will always have the
same full-scale range. Table 1 shows the capacitor value
selected for each range selection.
Table 1. Range Selection of the DDC118
RANGE2 RANGE1 RANGE0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CF
(pF, typ)
3
12.5
25
37.5
50
62.5
75
87.5
INPUT RANGE
(pC, typ)
−0.048 to 12
–0.2 to 50
–0.4 to 100
–0.6 to 150
–0.8 to 200
–0.1 to 250
–1.2 to 300
–1.4 to 350
SBAS325B − JUNE 2004 − REVISED APRIL 2009
Voltage Reference
The external voltage reference is used to reset the
integration capacitors before an integration cycle begins.
It is also used by the ∆Σ converter while the converter is
measuring the voltage stored on the integrators after an
integration cycle ends. During this sampling, the external
reference must supply the charge needed by the ∆Σ
converter. For an integration time of 400µs, this charge
translates to an average VREF current of approximately
150µA. The amount of charge needed by the ∆Σ converter
is independent of the integration time; therefore,
increasing the integration time lowers the average current.
For example, an integration time of 800µs lowers the
average VREF current to 75µA.
It is critical that VREF be stable during the different modes
of operation (see Figure 5). The ∆Σ converter measures
the voltage on the integrator with respect to VREF. Since
the integrator capacitors are initially reset to VREF, any
drop in VREF from the time the capacitors are reset to the
time when the converter measures the integrator output
will introduce an offset. It is also important that VREF be
stable over longer periods of time because changes in
VREF correspond directly to changes in the full-scale
range. Finally, VREF should introduce as little additional
noise as possible.
For these reasons, it is strongly recommended that the
external reference source be buffered with an operational
amplifier, as shown in Figure 6. In this circuit, the voltage
reference is generated by a 4.096V reference. A low-pass
filter to reduce noise connects the reference to an
operational amplifier configured as a buffer. This amplifier
should have low noise, and input/output common-mode
ranges that support VREF. Following the buffer are
capacitors placed close to the DDC118 VREF pin. Even
though the circuit in Figure 6 might appear to be unstable
because of the large output capacitors, it works well for
most operational amplifiers. It is NOT recommended that
series resistance be placed in the output lead to improve
stability since this can cause a drop in VREF, which
producing large offsets.
+5V
0.47µF
1
REF3140 ²
10kΩ
3
+
10µF
+5V
0.10µF
7
2
6
OPA350
3
0.10µF
4
+
10µF
0.1µF
To VREF
Pin 10 of
the DDC118
Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC118
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