OMAP3530_17 Datasheet, PDF (227/265 Pages) Texas Instruments – Applications Processors

OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 6-106. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode⁽¹⁾
NO.
PARAMETER
HSU0
f_p(CLK)
t_j(CLK)
hsusbx_tll_clk clock frequency
Jitter standard deviation⁽²⁾, hsusbx_tll_clk
HSU1 t_j(CLK)
Duty cycle, hsusbx_tll_clk pulse duration (low and high)
HSU6 t_d(CLKL-DIRV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid
t_{d(CLKL-DIRIV)} Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid
t_d(CLKL-NXTV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid
t_{d(CLKL-NXTIV)} Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid
HSU7 t_d(CLKL-DV)
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid
HSU8 t_d(CLKL-DIV)
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid
t_R(do)
Rise time, output signals
t_F(do)
Fall time, output signals
(1) In hsusbx, x is equal to 1, 2, or 3.
(2) The jitter probability density can be approximated by a Gaussian function.
1.15 V
MIN
MAX
60
200
47.6%
52.4%
9
0
9
0
4
0
2
2
UNIT
MHz
ps
ns
ns
ns
ns
ns
ns
ns
ns
HSU0
HSU1
HSU1
hsusbx_tll_clk
HSU3
HSU2
hsusbx_tll_stp
HSU6
HSU6
hsusbx_tll_dir_&_nxt
HSU5
HSU5
HSU8
HSU4
HSU4
HSU7
HSU7
hsusbx_tll_data[3:0]
Data_IN
Data_IN_(n+1)
In hsusbx, x is equal to 1, 2, or 3.
Data_IN_(n+2)
Data_OUT
Data_OUT_(n+1)
030-089
Figure 6-52. High-Speed USB – 8-bit TLL Master Mode
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 227
Submit Documentation Feedback
Product Folder Links: OMAP3530 OMAP3525