OMAPL138B-EP_16 Datasheet, PDF (222/284 Pages) Texas Instruments – OMAPL138B C6-Integra DSP ARM Processor

OMAPL138B-EP
SPRS815C – DECEMBER 2011 – REVISED APRIL 2013
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5.24.2 LCD Raster Mode
Table 5-112. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode⁽¹⁾
See Figure 5-63 through Figure 5-67
NO.
PARAMETER
1.3V, 1.2V, 1.1V
MIN
MAX
1.0V
MIN
MAX
UNIT
1 t_{c(PIXEL_CLK)}
Cycle time, pixel clock
26.66
33.33
ns
2 t_{w(PIXEL_CLK_H)}
Pulse duration, pixel clock high
10
10
ns
3 t_{w(PIXEL_CLK_L)}
Pulse duration, pixel clock low
10
10
ns
4 t_{d(LCD_D_V)}
Delay time, LCD_PCLK high to LCD_D[15:0] valid (write)
0
7
0
9
ns
5 t_{d(LCD_D_IV)}
Delay time, LCD_PCLK high to LCD_D[15:0] invalid
(write)
0
7
0
9
ns
6
t_{d(LCD_AC_ENB_CS_A)}
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high
0
7
0
9
ns
7
t_{d(LCD_AC_ENB_CS_I)}
Delay time, LCD_PCLK low to LCD_AC_ENB_CS low
0
7
0
9
ns
8 t_{d(LCD_VSYNC_A)} Delay time, LCD_PCLK low to LCD_VSYNC high
0
7
0
9
ns
9 t_{d(LCD_VSYNC_I)}
Delay time, LCD_PCLK low to LCD_VSYNC low
0
7
0
9
ns
10 t_{d(LCD_HSYNC_A)} Delay time, LCD_PCLK high to LCD_HSYNC high
0
7
0
9
ns
11 t_{d(LCD_HSYNC_I)}
Delay time, LCD_PCLK high to LCD_HSYNC low
0
7
0
9
ns
(1) Parameters are characterized from -40°C to 105°C unless otherwise noted.
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 5-63. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
222 Peripheral Information and Electrical Specifications
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