OMAPL138B-EP_16 Datasheet, PDF (194/284 Pages) Texas Instruments – OMAPL138B C6-Integra DSP ARM Processor

OMAPL138B-EP
SPRS815C – DECEMBER 2011 – REVISED APRIL 2013
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5.19 Universal Asynchronous Receiver/Transmitter (UART)
Each UART has the following features:
• 16-byte storage space for both the transmitter and receiver FIFOs
• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• Programmable auto-rts and auto-cts for autoflow control
• Programmable Baud Rate up to 12 MBaud
• Programmable Oversampling Options of x13 and x16
• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
• Prioritized interrupts
• Programmable serial data formats
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity bit generation and detection
– 1, 1.5, or 2 stop bit generation
• False start bit detection
• Line break generation and detection
• Internal diagnostic capabilities
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Modem control functions (CTS, RTS)
The UART registers are listed in Section 5.19.1
5.19.1 UART Peripheral Registers Description(s)
Table 5-89 is the list of UART registers.
UART0
BYTE ADDRESS
0x01C4 2000
0x01C4 2000
0x01C4 2004
0x01C4 2008
0x01C4 2008
0x01C4 200C
0x01C4 2010
0x01C4 2014
0x01C4 2018
0x01C4 201C
0x01C4 2020
0x01C4 2024
0x01C4 2028
0x01C4 2030
0x01C4 2034
UART1
BYTE ADDRESS
0x01D0 C000
0x01D0 C000
0x01D0 C004
0x01D0 C008
0x01D0 C008
0x01D0 C00C
0x01D0 C010
0x01D0 C014
0x01D0 C018
0x01D0 C01C
0x01D0 C020
0x01D0 C024
0x01D0 C028
0x01D0 C030
0x01D0 C034
Table 5-89. UART Registers
UART2
BYTE ADDRESS
0x01D0 D000
0x01D0 D000
0x01D0 D004
0x01D0 D008
0x01D0 D008
0x01D0 D00C
0x01D0 D010
0x01D0 D014
0x01D0 D018
0x01D0 D01C
0x01D0 D020
0x01D0 D024
0x01D0 D028
0x01D0 D030
0x01D0 D034
ACRONYM
REGISTER DESCRIPTION
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLH
REVID1
PWREMU_MGMT
MDR
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
Divisor LSB Latch
Divisor MSB Latch
Revision Identification Register 1
Power and Emulation Management Register
Mode Definition Register
194 Peripheral Information and Electrical Specifications
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