TMS320C6655_15 Datasheet, PDF (221/245 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
HEX ADDRESS
02C0 8A00
02C0 8A04
02C0 8A08
02C0 8A0C
02C0 8A10
02C0 8A14
02C0 8A18
02C0 8A1C
02C0 8A10
02C0 8A14
02C0 8A18
02C0 8A1C
02C0 8A90
02C0 8A94
02C0 8A98
02C0 8A9C
02C0 8AA0
02C0 8AA4
02C0 8AA8
02C0 8AAC
02C0 8B10
02C0 8B14
02C0 8B18
02C0 8B1C
Table 8-75. EMIC Control Registers
ACRONYM
IDVER
SOFT_RESET
EM_CONTROL
INT_CONTROL
C0_RX_THRESH_EN
C0_RX_EN
C0_TX_EN
C0_MISC_EN
C1_RX_THRESH_EN
C1_RX_EN
C1_TX_EN
C1_MISC_EN
C0_RX_THRESH_STAT
C0_RX_STAT
C0_TX_STAT
C0_MISC_STAT
C1_RX_THRESH_STAT
C1_RX_STAT
C1_TX_STAT
C1_MISC_STAT
C0_RX_IMAX
C0_TX_IMAX
C1_RX_IMAX
C1_TX_IMAX
REGISTER NAME
Identification and Version register
Software Reset Register
Emulation Control Register
Interrupt Control Register
Receive Threshold Interrupt Enable Register for CorePac0
Receive Interrupt Enable Register for CorePac0
Transmit Interrupt Enable Register for CorePac0
Misc Interrupt Enable Register for CorePac0
Receive Threshold Interrupt Enable Register for CorePac1 (C6657 only)
Receive Interrupt Enable Register for CorePac1 (C6657 only)
Transmit Interrupt Enable Register for CorePac1 (C6657 only)
Misc Interrupt Enable Register for CorePac1 (C6657 only)
Receive Threshold Masked Interrupt Status Register for CorePac0
Receive Interrupt Masked Interrupt Status Register for CorePac0
Transmit Interrupt Masked Interrupt Status Register for CorePac0
Misc Interrupt Masked Interrupt Status Register for CorePac0
Receive Threshold Masked Interrupt Status Register for CorePac1 (C6657
only)
Receive Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)
Transmit Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)
Misc Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)
Receive Interrupts Per Millisecond for CorePac0
Transmit Interrupts Per Millisecond for CorePac0
Receive Interrupts Per Millisecond for CorePac1 (C6657 only)
Transmit Interrupts Per Millisecond for CorePac1 (C6657 only)
8.18.3 EMAC Electrical Data/Timing (SGMII)
The Hardware Design Guide for KeyStone Devices (SPRABI2) specifies a complete EMAC and SGMII
interface solution for the C665x as well as a list of compatible EMAC and SGMII devices. TI has
performed the simulation and system characterization to ensure all EMAC and SGMII interface timings in
this solution are met; therefore, no electrical data/timing information is supplied here for this interface.
NOTE
TI supports only designs that follow the board design guidelines outlined in the application
report.
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Peripheral Information and Electrical Specifications 221
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