TMS320C6655_15 Datasheet, PDF (124/245 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
www.ti.com
8.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains
and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface
to control several important power and clock operations.
For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone
Devices User's Guide (SPRUGV4).
8.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power
dissipation. The global power/sleep controller (GPSC) is used to control the power gating of various power
domains.
Table 8-6 shows the C665x power domains.
DOMAIN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BLOCK(S)
Most peripheral logic
Per-core TETB and System TETB
Reserved
PCIe
SRIO
HyperLink
Reserved
MSMC RAM
Reserved
Reserved
Reserved
TCP3d
VCP2_B
C66x Core 0, L1/L2 RAMs
14
C66x Core 1, L1/L2 RAMs (C6657
only)
15
Reserved
Table 8-6. Power Domains
NOTE
Cannot be disabled
RAMs can be powered down
Reserved
Logic can be powered down
Logic can be powered down
Logic can be powered down
Reserved
MSMC RAM can be powered down
Reserved
Reserved
Reserved
RAMs can be powered down
RAMs can be powered down
L2 RAMs can sleep
L2 RAMs can sleep
Reserved
POWER CONNECTION
Always on
Software control
Reserved
Software control
Software control
Software control
Reserved
Software control
Reserved
Reserved
Reserved
Software control
Software control
Software control via C66x CorePac. For
details, see the C66x CorePac Reference
Guide.
Software control via C66x CorePac. For
details, see the C66x CorePac Reference
Guide.
Reserved
124 Peripheral Information and Electrical Specifications
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