TMS320C6655_15 Datasheet, PDF (123/245 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
8.2.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor
structures responsible for higher achievable clock rates and increased performance, comes an inevitable
penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently
of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type
and process technology. Higher clock rates also increase dynamic power, the power used when
transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O
activity.
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power
consumption while maintaining the device performance. SmartReflex in the C665x device is a feature that
allows the core voltage to be optimized based on the process corner of the device. This requires a voltage
regulator for each C665x device.
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is
required to be implemented whenever the C665x device is used. The voltage selection is done using 4
VCNTL pins which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices
application report and the Hardware Design Guide for KeyStone Devices (SPRABI2).
Table 8-5. SmartReflex 4-Pin VID Interface Switching Characteristics
(see Figure 8-3)
NO.
PARAMETER
MIN
1
td(VCNTL[2:0]-VCNTL[3])
Delay Time - VCNTL[2:0] valid after VCNTL[3] low
2
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low
0.07
3
td(VCNTL[2:0]-VCNTL[3])
Delay Time - VCNTL[2:0] valid after VCNTL[3] high
4
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high
0.07
5
VCNTL being valid to CVDD being switched to SmartReflex Voltage⁽²⁾
(1) C = 1/SYSCLK1 frequency (See Figure 8-9) in ms
(2) SmartReflex voltage must be set before execution of application code
MAX
300.00
172020C ⁽¹⁾
300.00
172020C
10
UNIT
ns
ms
ns
ms
ms
CVDD
VCNTL[3]
VCNTL[2:0]
1.1 V
SRV*
* SRV = Smart Reflex Voltage
4
5
1
3
LSB VID[2:0]
MSB VID[5:3]
2
Figure 8-3. SmartReflex 4-Pin VID Interface Timing
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Peripheral Information and Electrical Specifications 123
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