TMS320C6655_15 Datasheet, PDF (191/245 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
OFFSET
2D4h
2Dh
2E0h
2E4h
2E8h
2F0h
2F4h
2F8h
300h
304h
308h
NAME
PROG13_MPEAR
PROG13_MPPA
PROG14_MPSAR
PROG14_MPEAR
PROG14_MPPA
PROG15_MPSAR
PROG15_MPEAR
PROG15_MPPA
FLTADDRR
FLTSTAT
FLTCLR
Table 8-51. MPU4 Registers (continued)
DESCRIPTION
Programmable range 13, end address
Programmable range 13, memory page protection attributes
Programmable range 14, start address
Programmable range 14, end address
Programmable range 14, memory page protection attributes
Programmable range 15, start address
Programmable range 15, end address
Programmable range 15, memory page protection attributes
Fault address
Fault status
Fault clear
8.9.1.2 Device-Specific MPU Registers
8.9.1.2.1 Configuration Register (CONFIG)
The Configuration Register (CONFIG) contains the configuration value of the MPU.
Figure 8-27. Configuration Register (CONFIG)
31
24
ADDR_WIDTH
MPU0
R-0
MPU1
R-0
Reset Values MPU2
R-0
MPU3
R-0
MPU4
R-0
Legend: R = Read only; -n = value after reset
23
20
NUM_FIXED
R-0
R-0
R-0
R-0
R-0
19
16
NUM_PROG
R-16
R-5
R-16
R-1
R-16
15
12
NUM_AIDS
R-16
R-16
R-16
R-16
R-16
11 1
Reserved
R-0
R-0
R-0
R-0
R-0
0
ASSUME_ALLOWED
R-1
R-1
R-1
R-1
R-1
Table 8-52. Configuration Register (CONFIG) Field Descriptions
Bit
Field
31 – 24 ADDR_WIDTH
23 – 20 NUM_FIXED
19 – 16 NUM_PROG
15 – 12 NUM_AIDS
11 – 1 Reserved
0
ASSUME_ALLOWED
Description
Address alignment for range checking
• 0 = 1KB alignment
• 6 = 64KB alignment
Number of fixed address ranges
Number of programmable address ranges
Number of supported AIDs
Reserved. These bits will always reads as 0.
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines
whether the transfer is assumed to be allowed or not.
• 0 = Assume disallowed
• 1 = Assume allowed
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Peripheral Information and Electrical Specifications 191
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