TLC320AD535C-I_16 Datasheet, PDF (22/42 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

4.1.1 FS High Mode Primary Communication Timing
There are two possible modes for serial data transfer. One mode is the FS high mode which is selected by tying the
SI_SEL pin to DV_DD. Figure 4–2 shows the timing relationship for XX_SCLK, XX_FS, XX_DOUT and XX_DIN in a
primary communication for either the voice or data channel when in FS high mode. The timing sequence for this
operation is as follows:
1. XX_FS is brought high and remains high for one XX_SCLK period, then goes low.
2. A 16-bit word is transmitted from the ADC (DT_DOUT and VC_DOUT) and a 16-bit word is received for DAC
conversion (DT_DIN and VC_DIN).
XX_SCLK
XX_FS
XX_DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XX_DOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 4–2. FS High Mode Primary Serial Communication Timing
4.1.2 FS Low Mode Primary Communication Timing
The second possible serial interface mode is the FS low mode, which is selected by tying the SI_SEL pin to DV_SS.
This mode differs from the FS high mode in that the frame sync signal (FS) is active low, data transfer starts on the
falling edge of XX_FS, and XX_FS remains low throughout the data transfer. Figure 4–3 shows the timing relationship
for XX_SCLK, XX_FS, XX_DOUT and XX_DIN in a primary communication for either the voice or data channel when
in FS low mode. The timing sequence for this operation is as follows:
1. XX_FS is brought low by the TLC320AD535.
2. A 16-bit word is transmitted from the ADC (DT_DOUT and VC_DOUT) and a 16-bit word is received for DAC
conversion (DT_DIN and VC_DIN).
3. XX_FS is brought high signaling the end of the data transfer.
XX_SCLK
XX_FS
XX_DIN D15 D14 D13 D12 _D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XX_DOUT D15 D14 D13 D12 _{D11 D10} D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 4–3. FS Low Mode Primary Serial Communication Timing
4–2