TLC320AD535C-I_16 Datasheet, PDF (12/42 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

1.7 Terminal Functions (Continued)
TERMINAL
NAME
NO.
FLSH_IN
18
FLSH_OUT
17
HS_BUF
35
HS_REF
38
HSRX_FB
41
HSRXM
40
HSRXP
39
HSTX_IN
36
HSTX_OUT
37
MIC_AUDIO
55
MIC_BIAS
56
MONOUTM
60
MONOUTP
62
MVDD
61
MVSS
59
NC
POR
20
RESET
19
SI_SEL
33
SPKR_LEFT 51
SPKR_RIGHT 52
TAPI_IN
50
TAPI_OUT
49
TEST1
54
TEST2
53
VAVDD
48
VAVSS
45
VC_DIN
28
I/O
DESCRIPTION
I External logic input. When brought low FLSH_IN enables the FLSH_OUT output.
O Power output to write/erase flash EEPROM device (such as Intel 28F400B or AMD Am29F400). Outputs 5 V
(± 10%) at 45 mA maximum when FLSH_IN is brought low. FLSH_OUT does not go to a logic high state when
off. There is an internal NMOS pull down to maintain the specified voltage. An external pull down is not required.
O Handset buffer amplifier analog output. HS_BUF can be programmed for 0-dB gain or muted using the control
registers. This output is normally fed to the HSTX_IN terminal through an input resistor.
O Handset amplifier reference voltage HS_REF is set at 2.5 V for 5-V supply and 1.5 V for 3.3-V supply. The
maximum source current at this terminal is 2.5 mA.
O Feedback node for handset receive path amplifier. HSRX_FB is connected to the output of the handset receive
path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain
and filter poles.
I Handset receive path amplifier analog inverting input
I Handset receive path amplifier analog noninverting input
I Handset transmit amplifier analog inverting input. This node is normally fed by the HSBUF output through an
input resistor. The noninverting input of the amplifier is connected internally to 2.5 V for 5 V supply and 1.5 V
for 3.3 V supply.
O Handset transmit amplifier analog output
I Microphone preamplifier analog input. MIC_AUDIO can be programmed to add either 0-dB or 20-dB gain using
the control registers.
O Output that provides 2.5 V/1.5 V bias for electret microphone. The maximum source current at this terminal
is 5 mA.
O 8 Ω monitor speaker amplifier analog output. MONOUTM is set for 0-dB gain or is muted using the control
registers.
O 8 Ω monitor speaker amplifier analog output. MONOUTP is set for 0-dB gain or is muted using the control
registers.
I Monitor amplifier supply (5 V/3.3 V)
I Monitor amplifier ground
All terminals marked NC should be left unconnected.
O Power on reset signal. POR remains low while the 5-V supply at MVDD is below its threshold voltage and for
40 ms after it rises above the reset threshold.
I Codec device reset. RESET initializes all device internal registers to their default values. This signal is active
low.
I Serial interface mode select. When SI_SEL is tied to DVDD, the serial port is in FS high mode. When SI_SEL
is tied to DVSS, the serial port is in FS low mode (See Section 4, Serial Communications for more details).
O Analog output from 60-Ω speaker line amplifier. SPKR_LEFT is set for 0-dB gain or is muted using the control
registers.
O Analog output from 60-Ω speaker line amplifier. SPKR_RIGHT is set for 0-dB gain or is muted using the control
registers.
I Analog input to the TAPI (or sound card) preamplifier which can be programmed to add either 0 dB or 20 dB
gain via the control registers.
O TAPI buffer amplifier analog output. This 600-Ω amplifier is set for 0-dB gain or is muted using the control
registers.
I/O Test input/output port. TEST1 is for factory testing only and should be left unconnected.
I/O Test input/output port. TEST2 is for factory testing only and should be left unconnected.
I Voice channel analog power supply (5 V/3.3 V)
I Voice channel analog ground
I Voice channel digital data input. VC_DIN handles DAC input data as well as control register programming
information during the voice channel frame sync interval. VC_DIN is synchronized to VC_SCLK.
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