TLC320AD535C-I_16 Datasheet, PDF (11/42 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

1.6 Ordering Information
TA
0°C to 70°C
–40°C to 85°C
PACKAGE
PLASTIC QUAD FLATPACK (PM)
TLC320AD535
TLC320AD535I
1.7 Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
DAVDD
2 I Data channel analog power supply (5 V/3.3 V)
DAVSS
5 I Data channel analog ground
DREFM_ADC 7 O Data channel ADC voltage reference filter output. DREFM_ADC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_ADC
and DREFP_ADC. The nominal DC voltage at this terminal is 0 V.
DREFM_DAC 4 O Data channel DAC voltage reference filter output. DREFM_DAC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_DAC
and DREFP_DAC. The nominal dc voltage at this terminal is 0 V.
DREFP_ADC 6 O Data channel ADC voltage reference filter output. DREFP_ADC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_ADC
and DREFP_ADC. The dc voltage at this terminal is 3.375 V at 5-V DAVDD supply and 2.25 V at 3.3-V DAVDD
supply.
DREFP_DAC 3
DT_BUF
15
O Data channel DAC voltage reference filter output. DREFP_DAC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_DAC
and DREFP_DAC. The dc voltage at this terminal is 3.375 V at 5-DAVDD supply and 2.25 V at 3.3-DAVDD supply.
O Data channel buffer amp analog output. DT_BUF is programmed for 0-dB gain or is muted using the control
registers. This output is normally fed to the DTTX_IN terminal through an input resistor.
DT_DIN
26 I Data channel digital data input. DT_DIN handles DAC input data as well as control register programming
information during the data channel frame sync interval and is synchronized to DT_SCLK.
DT_DOUT
22 O Data channel digital data output. Data channel ADC output bits are transmitted during the data channel frame
sync period that is synchronized to DT_SCLK. DT_DOUT is at high impedance when DT_FS is not activated.
DT_FS
21 O Data channel serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data and receiving
of DAC data in the data channel. This signal can be active high (FS high mode) or active low (FS low mode)
depending on the voltage applied to SI_SEL (See Section 4, Serial Communications for more details).
DT_MCLK
27 I Data channel master clock input. All of the internal clocks for the data channel are derived from this clock.
DT_REF
DTRX_FB
12 O Handset amplifier reference voltage. The voltage at this pin is set at 2.5 V for a 5-V DAVDD supply and 1.5 V for
a 3.3-V DAVDD supply. The maximum source current at this terminal is 2.5 mA.
9 O Data channel receive path amplifier feedback node. DTRX_FB connects to the output of the data channel receive
path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain
and filter poles.
DTRXM
10 I Data channel receive path amplifier analog inverting input
DTRXP
11 I Data channel receive path amplifier analog noninverting input.
DT_SCLK
25 O Data channel shift clock signal. This signal clocks serial data into DT_DIN and out of DT_DOUT during the data
channel frame-sync interval. DT_SCLK = DT_MCLK/2
DTTX_IN
14 I Data channel transmit amplifier analog inverting input. This node is normally fed by the DT_BUF output through
an input resistor. The noninverting input of the amplifier is connected internally to 2.5 V for 5 V supply and 1.5
V for 3.3 V supply.
DTTX_OUT
13 O Data channel transmit amplifier analog output
DVDD
DVSS
FILT
24 I Digital power supply (5 V/3.3 V).
23 I Digital ground
57 O Bandgap filter node. FILT provides decoupling of the 3.375-V bandgap reference. The optimal capacitor value
is 0.1 µF (ceramic). This node should not be used as a voltage source.
1–5