TLC320AD535C-I_16 Datasheet, PDF (18/42 Pages) Texas Instruments – DUAL CHANNEL VOICE/DATA CODEC

3.6 Sigma-Delta DAC
Each DAC is an oversampling sigma-delta modulator. The DAC performs high-resolution, low-noise digital-to-analog
conversion using oversampling sigma-delta techniques.
3.7 Interpolation Filter
Each interpolation filter resamples the digital data at a rate of N times the incoming sample rate, where N is the
oversampling ratio. The high-speed data output from this filter is then applied to the sigma-delta DAC.
3.8 Analog and Digital Loopbacks
The test capabilities include an analog loopback and digital loopback. The loopbacks provide a means of testing the
ADC/DAC channels and are used for in-circuit system-level tests. The loopback feeds the ADC output to the DAC
input on the IC for each individual channel. The analog loopback functions test only the codec portions of the device
and do not include the hybrid amplifiers.
Analog loopback loops the DAC output back into the ADC input of the same channel. Digital loopback loops the ADC
output back into the DAC input of the respective channel. Analog loopback is enabled by setting the D4 bit in the
control register 1 for the data channel or control register 3 for the voice channel. Digital loopback is enabled by setting
the D5 bit high in control register 1 for the data channel or control register 3 for the voice channel.
3.9 Software Power Down
The software power down resets all internal counters, but leaves the contents of the programmable control registers
unchanged for the selected channel. The device has separate and independent software power down bits for the
voice and data channels. The software power down feature is invoked by setting the D6 bit high in control register
1 for the data channel or setting the D6 bit in control register 3 for the voice channel. There is no hardware power
down function in the TLC320AD535.
3.10 Reset Circuit
This circuit monitors the 5-V MV_DD power supply coming into the device from the bus and asserts an active low
power-on-reset ( POR) signal whenever this supply voltage drops below its threshold voltage. The reset signal
remains low while the supply voltage is below the threshold voltage. It remains low for 40 ms (nominal) after the supply
voltage has risen above the reset threshold voltage. Once the voltage rises above the threshold, an internal counter
is activated and holds the POR signal low for an additional 40 ms (nominal). The signal then goes high and remains
high as long as the MV_DD supply remains in the acceptable voltage range. This circuit is, in effect, on initial power
up of the device and POR is held low until the supply voltage rises above the threshold. In addition, a reset is triggered
if a transient spike of sufficient magnitude and duration occurs. The supply must drop below the threshold voltage
for a period of time greater than the delay time shown in the following table (delay time, MV_DD to reset). If a spike
occurs that drops below the threshold, but the supply voltage returns above the threshold within the delay time, POR
remains in the high state.
3–2