THS3092_14 Datasheet, PDF (22/45 Pages) Texas Instruments – HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS

THS3092
THS3096
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
• Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an R_S since the THS3092/6 are nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss
intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is not necessary onboard, and
in fact, a higher impedance environment
improves distortion as shown in the distortion
versus load plots. With a characteristic board
trace impedance based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS3092/6 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the
trace impedance. If the 6-dB attenuation of a
doubly terminated transmission line is
unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
• Socketing a high speed part like the THS3092/6
are not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS3092/6 parts directly onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS3092/6 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
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leadframe upon which the die is mounted [see
Figure 66(a) and Figure 66(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 66(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS3092/6 have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
Side View (a)
DIE
Thermal
Pad
End View (b)
Bottom View (c)
Figure 66. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
Pin 1
0.300
0.100
0.035
0.026
0.010
0.060
0.140
0.060
0.030
0.050 _0.176
0.010
vias
0.035
0.080
Top View
Figure 67. DDA PowerPAD PCB Etch and Via
Pattern
22
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