THS3092_14 Datasheet, PDF (21/45 Pages) Texas Instruments – HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS

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and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3096
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for disable
PD ≥ REF + 2.0 V for enable
where the usable range at the REF pin is V_S– ≤ V_REF≤
(V_S+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
thresholds to V_midrail + 2 V and V_midrail + 0.8 V
respectively.
Table 2. Power-Down Threshold Voltage Levels
SUPPLY
VOLTAGE
(V)
±15, ±5
±15
±15
±5
±5
30
10
REFERENCE
PIN VOLTAGE
(V)
0.0
2.0
–2.0
1.0
–1.0
15
5.0
ENABLE
LEVEL
(V)
2.0
4.0
0.0
3.0
1.0
17
7.0
DISABLE
LEVEL
(V)
0.8
2.8
–1.2
1.8
–0.2
15.8
5.8
Note that if the REF pin is left unterminated, it will
float to the positive rail and will fall outside of the
recommended operating range given above V_S– ≤
V_REF ≤ (V_S+ – 4 V). As a result, it will no longer serve
as a reliable reference for the PD pin, and the
enable/disable thresholds given above will no longer
apply. If the PD pin is also left unterminated, it will
also float to the positive rail and the device will be
enabled. If balanced, split supplies are used (±V_S)
and the REF and PD pins are grounded, the device
will be disabled.
THS3092
THS3096
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier, like the THS3092/6, requires careful
attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
• Careful selection and placement of external
components preserve the high frequency
performance of the THS3092/6. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Again, keep their leads and PC board
trace length as short as possible. Never use
wirebound type resistors in a high frequency
application. Since the output pin and inverting
input pins are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistors, if any, as close as
possible to the inverting input pins and output
pins. Other network components, such as input
termination resistors, should be placed close to
the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible,
consistent with load driving considerations.
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