LP3958 Datasheet, PDF (22/36 Pages) National Semiconductor (TI) – Lighting Management Unit with High Voltage Boost Converter

LP3958
SNVS423C – JANUARY 2006 – REVISED MARCH 2013
ack from slave
ack from slave
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ack from slave
start msb Chip Address lsb w ack msb Register Add lsb ack
msb DATA lsb
ack stop
SCL
SDA
start id = 59H = 101 1001b w ack
addr = 02H
ack
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 59H (101 1001b) for LP3958.
Figure 25. I²C Write Cycle
address 02H data
ack stop
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb w
msb Register Add lsb
rs msb Chip Address lsb r
msb DATA lsb
stop
SCL
SDA
start id = 59H = 101 1001b w ack
addr = 00H
ack rs id = 59H = 101 1001b r ack address 00H data ack stop
Figure 26. I²C Read Cycle
SDA
8
SCL
1
7
6
2
8
1
5
3
4
Figure 27. I²C Timing Diagram
10
7
9
I²C TIMING PARAMETERS (V_DD1,2 = 3.0 to 4.5V, V_DDIO = 1.8V to V_DD1,2)
Symbol
Parameter
1
Hold Time (repeated) START Condition
Limit ⁽¹⁾
Min
Max
0.6
Unit
µs
(1) Data guaranteed by design
22
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