LP3958 Datasheet, PDF (20/36 Pages) National Semiconductor (TI) – Lighting Management Unit with High Voltage Boost Converter

LP3958
SNVS423C – JANUARY 2006 – REVISED MARCH 2013
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Name
DATA[2:0]
GPIO DATA (07H)
Bit
2:0
Description
Data bits
GPIO control register is used to set the direction of each GPIO pin. For example, by setting OEN0 bit high the
GPIO[0]/PWM pin acts as a logic output pin with data defined DATA0 in GPIO data register. Note, that the
EN_PWM_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to act as PWM input. GPIO[1] and GPIO[2]
pins can be selected to be inputs or outputs, defined by OEN1 and OEN2 bit status. PWM functionality is valid
only for GPIO[0]/PWM pin. GPIO data register contains the data of GPIO pins. When output direction is selected
to GPIO pin, then GPIO data register defines the output pin state. When GPIO data register is read, it contains
the state of the pin despite of the pin direction.
Table 4. Logic Interface Characteristics(V_DDIO = 1.65V...V_DD1,2 unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
LOGIC INPUT SCL, SDA, GPIO[0:2]
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
f_SCL
Clock Frequency
LOGIC INPUT NRST
0.8×V_DDIO
−1.0
0.2×V_DDIO
V
V
1.0
µA
400
kHz
V_IL
Input Low Level
V_IH
Input High Level
I_I
Input Current
t_NRST
Reset Pulse Width
LOGIC OUTPUT SDA
0.5
V
1.2
V
-1.0
1.0
µA
10
µs
V_OL
Output Low Level
V_OH
Output High Level
I_L
Output Leakage Current
LOGIC OUTPUT GPIO[0:2]
I_SDA = 3mA
I_SDA = -3mA
V_SDA = 2.8V
0.3
0.5
V
V_DDIO − 0.5 V_DDIO − 0.3
1.0
µA
V_OL
Output Low Level
V_OH
Output High Level
I_L
Output Leakage Current
I_GPIO = 3 mA
I_GPIO = −3 mA
V_GPIO = 2.8V
0.3
0.5
V
V_DDIO − 0.5 V_DDIO − 0.3
V
1.0
µA
I²C Compatible Interface
I²C SIGNALS
The SCL pin is used for the I²C clock and the SDA pin is used for bidirectional data transfer. Both these signals
need a pull-up resistor according to I²C specification.
I²C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 22. I²C Signals: Data Validity
20
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