LMH6622 Datasheet, PDF (22/33 Pages) National Semiconductor (TI) – Dual Wideband, Low Noise, 160MHz, Operational Amplifiers

LMH6622
SNOS986E – DECEMBER 2001 – REVISED JULY 2014
10 Power Supply Recommendations
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10.1 Driving Capacitive Load
Capacitive Loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier
becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to
overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed
between the load and the output. In general, the bigger the isolation resistor, the more damped the pulse
response becomes. For initial evaluation, a 50 Ω isolation resistor is recommended.
11 Layout
11.1 Layout Guidelines
11.1.1 Circuit Layout Considerations
Texas Instruments suggests the copper patterns on the evaluation boards listed below as a guide for high
frequency layout. These boards are also useful as an aid in device testing and characterization. As is the case
with all high-speed amplifiers, accepted-practice R_F design technique on the PCB layout is mandatory. Generally,
a good high frequency layout exhibits a separation of power supply and ground traces from the inverting input
and output pins. Parasitic capacitances between these nodes and ground will cause frequency response peaking
and possible circuit oscillations (see SNOA367, Application Note OA-15, for more information). High quality chip
capacitors with values in the range of 1000 pF to 0.1 μF should be used for power supply bypassing. One
terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a point
that is as close as possible to each supply pin as allowed by the manufacturer's design rules. In addition, a
tantalum capacitor with a value between 4.7 μF and 10 μF should be connected in parallel with the chip
capacitor. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize
inductance and microstrip line effect. Input and output termination resistors should be placed as close as
possible to the input/output pins. Traces greater than 1 inch in length should be impedance matched to the
corresponding load termination.
Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained so
as to minimize the imbalance of amplitude and phase of the differential signal.
DEVICE
LMH6622MA
LMH6622MM
PACKAGE
SOIC-8
VSSOP-8
EVALUATION BOARD P/N
LMH730036
LMH730123
Component value selection is another important parameter in working with high speed/high performance
amplifiers. Choosing external resistors that are large in value compared to the value of other critical components
will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board
layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.
Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low
value resistors could load down nodes and will contribute to higher overall power dissipation and worse
distortion.
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