LMH6550 Datasheet, PDF (22/33 Pages) National Semiconductor (TI) – Differential, High Speed Op Amp

LMH6550
SNOSAK0I – DECEMBER 2004 – REVISED JANUARY 2015
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10 Power Supply Recommendations
The LMH6550 can be used with any combination of positive and negative power supplies as long as the
combined supply voltage is between 4.5 V and 12 V. The LMH6550 will provide best performance when the
output voltage is set at the mid supply voltage, and when the total supply voltage is between 9 V and 12 V.
When selecting a supply voltage that is less than 9 V it is important to consider both the input common-mode
voltage range as well as the output voltage range.
Power supply bypassing as shown in Figure 23 and Figure 24 is important and power supply regulation should
be within 5% or better when using a supply voltage near the edges of the operating range.
11 Layout
11.1 Layout Guidelines
The LMH6550 is a very high performance amplifier. To get maximum benefit from the differential circuit
architecture, board layout and component selection is very critical. The circuit board should have low a
inductance ground plane and well bypassed broad supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the amplifier as
should the supply bypass capacitors. The LMH730154 evaluation board is an example of good layout
techniques.
The LMH6550 is sensitive to parasitic capacitances on the amplifier inputs and to a lesser extent on the outputs
as well. Ground and power plane metal should be removed from beneath the amplifier and from beneath R_F and
R_G.
With any differential signal path, symmetry is very important. Even small amounts of asymmetry will contribute to
distortion and balance errors.
TI offers evaluation boards to aid in device testing and characterization and as a guide for proper layout.
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers,
SNOA367, for more information).
11.2 Layout Example
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Figure 34. EVM Layout (Top)
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