TMS320TCI6484 Datasheet, PDF (214/242 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6484
Communications Infrastructure Digital Signal Processor
SPRS438E—October 2009
Table 8-109 Timing Requirements for UTOPIA Slave Receive
(see Figure 8-49)
No.
1 t_{su(URDV-URCH)}
2 t_h(URCH-URDV)
3 t_{su(URAV-URCH)}
4 t_h(URCH-URAV)
9 t_{su(URENBL-URCH)}
10 t_{h(URCH-URENBL)}
11 t_{su(URSH-URCH)}
12 t_h(URCH-URSH)
End of Table 8-109
Setup time, URDATA valid before URCLK high
Hold time, URDATA valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
Min
4
1
4
1
4
1
4
1
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Max Unit
ns
ns
ns
ns
ns
ns
ns
ns
Table 8-110 Switching Characteristics for UTOPIA Slave Receive Cycles ⁽¹⁾
(see Figure 8-49)
No.
Parameter
5 t_{d(URCH-URCLAV)}
Delay time, URCLK high to URCLAV driven active value
6 t_{d(URCH-URCLAVL)}
Delay time, URCLK high to URCLAV driven inactive low
7 t_{d(URCH-URCLAVHZ)} Delay time, URCLK high to URCLAV going Hi-Z
8 t_{w(URCLAVL-URCLAVHZ)} Pulse duration (low), URCLAV low to URCLAV Hi-Z
End of Table 8-110
1 Over recommended operating conditions.
Figure 8-49 UTOPIA Slave Receive Timing^(A)
URCLK
2
1
URDATA[7:0]
P48
H1
URADDR[4:0] N
0x1F
3
N+1
4
0x1F
URCLAV
URENB
URSOC
N
10
5
N+1
9
11
H2
N+2
7
8
6
12
Min
Max Unit
3
12 ns
3
12 ns
9
18.5 ns
3
ns
H3
0x1F
N+2
(A) The UTOPIA slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC signals).
214 C64x+ Peripheral Information and Electrical Specifications
Copyright © 2009 Texas Instruments Incorporated