TMS320TCI6484 Datasheet, PDF (153/242 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6484
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS438E—October 2009
8.7.3.9 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Table 8-43 and
described in Table 8-44.
Table 8-43 PLL Controller Status Register (PLLSTAT)
Address - 029A 013C
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
Acronym
Reset ⁽¹⁾
Reserved
R-0
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Acronym
Reset ⁽¹⁾
Reserved
R-0
GOSTAT
R-0
1 R/W = Read/Write; R = Read only; -n = value after reset
Table 8-44 PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit Acronym
31:1
Reserved
0
GOSTAT
End of Table 8-44
Description
Reserved. Read only. Always reads as 0. Writes have no effect.
GO operation status.
0 = GO operation is not in progress. SYSCLK divide ratios are not being changed.
1 = GO operation is in progress. SYSCLK divide ratios are being changed.
Copyright © 2009 Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 153