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| TMS320TCI6484 Datasheet, PDF (175/242 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor | |||
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www.ti.com
Figure 8-26 I2C Receive Timings
11
SDA
SCL
8
4
10
1
3
Stop Start
TMS320TCI6484
Communications Infrastructure Digital Signal Processor
SPRS438EâOctober 2009
6
5
9
14
13
12
7
3
2
Repeated
Start
Stop
Table 8-68 Switching Characteristics for I2C Timings (1)
(see Figure 8-27)
No.
16 tc(SCL)
17 tsu(SCLH-SDAL)
18 th(SDAL-SCLL)
19 tw(SCLL)
20 tw(SCLH)
21 td(SDAV-SDLH)
22 tv(SDLL-SDAV)
23 tw(SDAH)
24 tr(SDA)
25 tr(SCL)
26 tf(SDA)
27 tf(SCL)
28 td(SCLH-SDAH)
29 Cp
End of Table 8-68
Parameter
Cycle time, SCL
Setup time, SCL high to SDA low (for a repeated START
condition)
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I2C bus devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
Standard Mode
Min
Max
10
4.7
4
4.7
4
250
0
4.7
1000
1000
300
300
4
10
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Fast Mode
Min
2.5
Max Unit
ms
0.6
ms
0.6
1.3
0.6
100
0
1.3
20 + 0.1Cb (1)
20 + 0.1Cb (1)
20 + 0.1Cb (1)
20 + 0.1Cb (1)
0.6
ms
ms
ms
ns
0.9 ms
ms
300 ns
300 ns
300 ns
300 ns
ms
10 pF
Copyright © 2009 Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 175
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