THS3201-EP_14 Datasheet, PDF(21/34 Page) Texas Instruments – 1.8-GHz LOW-DISTORTION CURRENT-FEEDBACK AMPLIFIER

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THS3201-EP

www.ti.com ..................................................................................................................................................... SGLS283B â APRIL 2005 â REVISED JANUARY 2009

Printed-Circuit Board Layout Techniques for

Optimal Performance

Achieving optimum performance with high-frequency

amplifier-like devices in the THS3201 requires careful

attention to board layout parasitic and external

component types.

Recommendations that optimize performance include:

â¢ Minimize parasitic capacitance to any power or

ground plane for the negative input and ouput pins

by voiding the area directly below these pins and

connecting traces and the feedback path.

Parasitic capacitance on the output and negative

input pins can cause instability. To reduce

unwanted capacitance, a window around the

signal I/O pins should be opened in all of the

ground and power planes around those pins and

the feedback path. Otherwise, ground and power

planes should be unbroken elsewhere on the

board.

â¢ Minimize the distance (<0.25 in) from the

power-supply pins to high frequency 0.1-ÂµF and

100-pF decoupling capacitors. At the device pins,

the ground and power-plane layout should not be

in close proximity to the signal I/O pins. Avoid

narrow power and ground traces to minimize

inductance between the pins and the decoupling

capacitors. The power-supply connections should

always be decoupled with these capacitors.

Larger (6.8 ÂµF or more) tantalum decoupling

capacitors, effective at lower frequency, should

also be used on the main supply pins. These may

be placed somewhat farther from the device and

may be shared among several devices in the

same area of the PC board. The primary goal is to

minimize the impedance seen in the

differential-current return paths. For driving

differential loads with the THS3201, adding a

capacitor between the power-supply pins

improves 2nd order harmonic distortion

performance. This also minimizes the current loop

formed by the differential drive.

â¢ Careful selection and placement of external

components preserve the high frequency

performance of the THS3201. Resistors should be

a low-reactance type. Surface-mount resistors

work best and allow a tighter overall layout. Again,

keep their leads and PC board trace length as

short as possible. Never use wirebound-type

resistors in a high-frequency application. Since the

output pin and inverting input pins are the most

sensitive to parasitic capacitance, always position

the feedback and series output resistors, if any, as

close as possible to the inverting input pins and

output pins. Other network components, such as

input termination resistors, should be placed close

to the gain-setting resistors. Even with a

low-parasitic capacitance shunting the external

resistors, excessively high resistor values can

create significant time constants that can degrade

performance. Good axial metal-film or

surface-mount resistors have approximately

0.2 pF in shunt with the resistor. For resistor

values >2 kâ¦, this parasitic capacitance can add a

pole and/or a zero that can effect circuit operation.

Keep resistor values as low as possible,

consistent with load driving considerations.

â¢ Connections to other wideband devices on the

board may be made with short direct traces or

through onboard transmission lines. For short

connections, consider the trace and the input to

the next device as a lumped capacitive load.

Relatively wide traces (50 mils to 100 mils) should

be used, preferably with ground and power planes

opened up around them. Estimate the total

capacitive load and determine if isolation resistors

on the outputs are necessary. Low parasitic

capacitive loads (<4 pF) may not need an RS

since the THS3201 is nominally compensated to

operate with a 2-pF parasitic load. Higher parasitic

capacitive loads without an RS are allowed as the

signal gain increases (increasing the unloaded

phase margin). If a long trace is required and the

6-dB signal loss intrinsic to a doubly-terminated

transmission line is acceptable, implement a

matched impedance transmission line using

microstrip or stripline techniques (consult an ECL

design handbook for these techniques).

â¢ A 50-â¦ environment is not necessary onboard

and, in fact, a higher-impedance environment

improves distortion as shown in the distortion

versus load plots. With a characteristic board

trace impedance based on board material and

trace dimensions, a matching series resistor into

the trace from the output of the THS3201 is used,

as well as a terminating shunt resistor at the input

of the destination device.

â¢ Remember also that the terminating impedance is

the parallel combination of the shunt resistor and

the input impedance of the destination device; this

total effective impedance should be set to match

the trace impedance. If the 6-dB attenuation of a

doubly-terminated transmission line is

unacceptable, a long trace can be

series-terminated at the source end only. Treat

the trace as a capacitive load in this case. This

does not preserve signal integrity as well as a

doubly-terminated line. If the input impedance of

the destination device is low, there is some signal

attenuation due to the voltage divider formed by

the series output into the terminating impedance.

â¢ Socketing a high-speed part such as the THS3201

is not recommended. The additional lead length

and pin-to-pin capacitance introduced by the

socket can create an extremely troublesome

parasitic network, which can make it almost

Product Folder Link(s): THS3201-EP

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