LM3450 Datasheet, PDF (21/40 Pages) National Semiconductor (TI) – LED Driver with Active Power Factor Correction and Phase Dimming Decoder

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LM3450
SNVS681D – NOVEMBER 2010 – REVISED MAY 2013
1.2
1.0
VADJ=3V
2.5V
0.8
2V
0.6
1.5V
0.4
1V
0.2
0.5V
0.0
0.0 0.2 0.4 0.6 0.8 1.0
LM3450/A DEMODULATED VAC PIN DUTY CYCLE
Figure 30. Complete Decoder Mapping
Since the buffered decoder output has amplitude equal to V_ADJ and the resulting PWM signal is filtered into an
analog voltage at FLT2, the V_ADJ pin can be used to change the mapping as shown in Figure 30. The maximum
LED current (DIM = 0) when V_ADJ = 3V corresponds to decoded angles of 70% or greater. Some dimmers have a
maximum angle greater than this. If V_ADJ is reduced to 2.5V, the maximum LED current will correspond to an
angle of 80% and at V_ADJ = 2V the maximum will occur at a decoded angle of 95%.
The V_ADJ pin can also be used to implement a standard analog adjust function. If the demodulated phase angle
at V_AC is above 85%, then the fast filter is always enabled (500kΩ shorted) and the V_ADJ pin can solely be used
to scale the DIM pin duty cycle. When V_ADJ is pulled below 75mV the part enters low power shutdown so the
maximum attainable contrast ratio using V_ADJ only is approximately 40:1.
Both FLT1 and FLT2 have pull-down MosFETs that are turned on when V_CC UVLO falling threshold is triggered.
This provides a quick discharge path for the capacitors and eliminates the possibility of an undesired light level at
the next startup.
Rectified AC
R_BS
Q_PS
10k
AC
AC
NTC
Connect if thermal
Q_PS
thermal
3904
protection circuit is
not desired
protection _15k
circuit
R_HLD
C_HLD
BIAS
LM3450/50A
HOLD
5 P$
+
-
Sample
I_SEN
40 k:
GND
-
V_SEN
+
R_SEN
C_SEN
Figure 31. Dynamic Hold Circuit
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