LM3450 Datasheet, PDF (20/40 Pages) National Semiconductor (TI) – LED Driver with Active Power Factor Correction and Phase Dimming Decoder

LM3450
SNVS681D – NOVEMBER 2010 – REVISED MAY 2013
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V_ADJ
V_FLT2
V_FLT1
Figure 28. FLT1 to FLT2 Mapping
The FLT1 signal is routed through a 2 pole low pass filter (R_F1, C_F1, R_F2, C_F2), as shown in Figure 26, to remove
the twice line frequency ripple. The resulting analog signal at FLT2 is compared to a 500Hz Triangle wave to
create the inverted PWM signal at the DIM pin as shown in Figure 29:
V_FLT2
V_DIM
Figure 29. FLT2 to DIM Mapping
This PWM signal at the DIM pin can be used as the dim input to a secondary LED driver. DIM is an open drain
output designed for isolated solutions. Optical isolation is used to transmit signals across the isolation boundary.
With most opto-isolators, the edge rate is dependent on the amount of drive current through the photodiode. The
open-drain configuration allows the primary bias supply (V_CC) to provide the current as shown in Figure 26. The
choice of resistor (R_PB) between V_CC and the photodiode anode will set the drive current. This enables the user
to trade-off PWM accuracy with system efficiency.
The open drain configuration also ensures that the secondary has a resistor from the phototransistor’s emitter to
secondary ground (not from collector to secondary bias). During system turn-off, this prevents an undesired LED
blink because the secondary stage LED driver is forced off.
A variable sample rate and dynamic filter ensure fast, smooth dimming transitions (movement of the dimmer)
while maintaining robust flicker-free behavior when the dimmer is static. The sample rate depends on past and
present angle information. The dynamic filter is a dual mode filter. During standby mode, when a transition has
not been made and the dimmer is static, a 500kΩ series resistor is connected between the buffered output and
FLT1 as shown in Figure 26.
The 500kΩ resistor is shorted when the LM3450/50A senses a large transition of the dimmer. This increases the
filter speed while the dimmer is transitioning between levels to improve response time.
The FLT1 and FLT2 poles created by each RC pair (R_F1 and C_F1, R_F2 and C_F2) should be set as follows:
• C_F1 and C_F2 can be 1µF ceramic capacitors for all designs.
• R_F1 and R_F2 should be set between 15kΩ (~10Hz) and 75kΩ (~2Hz).
2 Hz poles provide a “smooth fade” while 10Hz poles create a “snappy” response.
These component values ensure that the static filter condition in standby mode has 1 pole approximately a
decade lower than the nominal in order to provide good noise immunity to the system.
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