TLC59116F_15 Datasheet, PDF (20/38 Pages) Texas Instruments – 16-Channel Fast-Mode Plus I2C Bus LED Driver

TLC59116F
SCLS714C – MARCH 2009 – REVISED SEPTEMBER 2015
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8.6.2.3 Individual Brightness Control (PWM0–PWM15) Registers
Table 5. PWM0–PWM15 – Individual Brightness Control Registers (Address 02h to 11h) Bit Description
ADDRESS REGISTER BIT
SYMBOL
ACCESS ⁽¹⁾
VALUE ⁽²⁾
DESCRIPTION
02h
PWM0
7:0
IDC0[7:0]
R/W
0000 0000
PWM0 individual duty cycle
03h
PWM1
7:0
IDC1[7:0]
R/W
0000 0000
PWM1 individual duty cycle
04h
PWM2
7:0
IDC2[7:0]
R/W
0000 0000
PWM2 individual duty cycle
05h
PWM3
7:0
IDC3[7:0]
R/W
0000 0000
PWM3 individual duty cycle
06h
PWM4
7:0
IDC4[7:0]
R/W
0000 0000
PWM4 individual duty cycle
07h
PWM5
7:0
IDC5[7:0]
R/W
0000 0000
PWM5 individual duty cycle
08h
PWM6
7:0
IDC6[7:0]
R/W
0000 0000
PWM6 individual duty cycle
09h
PWM7
7:0
IDC7[7:0]
R/W
0000 0000
PWM7 individual duty cycle
0Ah
PWM8
7:0
IDC8[7:0]
R/W
0000 0000
PWM8 individual duty cycle
0Bh
PWM9
7:0
IDC9[7:0]
R/W
0000 0000
PWM9 individual duty cycle
0Ch
PWM10
7:0
IDC10[7:0]
R/W
0000 0000
PWM10 individual duty cycle
0Dh
PWM11
7:0
IDC11[7:0]
R/W
0000 0000
PWM11 individual duty cycle
0Eh
PWM12
7:0
IDC12[7:0]
R/W
0000 0000
PWM12 individual duty cycle
0Fh
PWM13
7:0
IDC13[7:0]
R/W
0000 0000
PWM13 individual duty cycle
10h
PWM14
7:0
IDC14[7:0]
R/W
0000 0000
PWM14 individual duty cycle
11h
PWM15
7:0
IDC15[7:0]
R/W
0000 0000
PWM15 individual duty cycle
(1) R = read, W = write
(2) Default value
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
IDCx[7:0]
Duty cycle =
256
(1)
8.6.2.4 Group Duty Cycle Control (GRPPWM) Register
Table 6. GRPPWM – Group Duty Cycle Control Register (Address 12h) Bit Description
ADDRESS REGISTER BIT
SYMBOL
ACCESS ⁽¹⁾
VALUE ⁽²⁾
DESCRIPTION
12h
GRPPWM 7:0
GDC0[7:0]
R/W
1111 1111
GRPPWM register
(1) R = read, W = write
(2) Default value
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed frequency signal is
superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness
control allowing the LED outputs to be dimmed with the same value.
NOTE
The value in GRPFREQ has to be programmed to 00h when DMBLNK = 0.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED
output off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx
= 11 (LEDOUT0 to LEDOUT3 registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle
(ON/OFF ratio in percentages).
GDC[7:0]
Duty cycle =
256
(2)
20
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