TLC59116F_15 Datasheet, PDF (13/38 Pages) Texas Instruments – 16-Channel Fast-Mode Plus I2C Bus LED Driver

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Programming (continued)
TLC59116F
SCLS714C – MARCH 2009 – REVISED SEPTEMBER 2015
R/W
1
1
0
1
0
1
1
0
The software reset I²C bus address is reserved address and cannot be use as regular I²C bus slave address or as an
LED All-Call or LED Sub-Call address.
Figure 9. Software Reset Address
8.5.6 Characteristics of the I²C Bus
The I²C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply through a pullup
resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not
busy.
8.5.6.1 Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 10).
SDA
SCL
Data line stable;
data valid
Change of
data
allowed
Figure 10. Bit Transfer
8.5.6.2 START and STOP Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the START condition (S). A low-to-high transition of the data line while the clock is
high is defined as the STOP condition (P) (see Figure 11).
SDA
SDA
SCL
S
SCL
P
START Condition
STOP Condition
Figure 11. Definition of START and STOP Conditions
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