SN74AUP1G80_16 Datasheet, PDF (2/25 Pages) Texas Instruments – LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74AUP1G80
SCES593E – JULY 2004 – REVISED MAY 2010
www.ti.com
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
3.3-V
L^Lo^Vg^Cic^†
20%
20%
0%
AUP
0%
† _{Single, dual, and triple gates}
AUP
Figure 1. AUP – The Lowest-Power Family
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 ^Input
1.5
1
Output
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART
NUMBER
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YFP
Reel of 3000
SN74AUP1G80YFPR
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUP1G80YZPR
QFN – DRY
Reel of 5000
SN74AUP1G80DRYR
uQFN – DSF
Reel of 5000
SN74AUP1G80DSFR
SOT (SOT-23) – DBV
Reel of 3000
Reel of 250
SN74AUP1G80DBVR
SN74AUP1G80DBVT
SOT (SC-70) – DCK
Reel of 3000
Reel of 250
SN74AUP1G80DCKR
SN74AUP1G80DCKT
TOP-SIDE
MARKING ⁽³⁾
_ _ _HX_
_ _ _HX_
HX
HX
H80_
HX_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
CLK
D
OUTPUT
Q
↑
H
L
↑
L
H
L or H
X
Q₀
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK
D
CLK
Q
Q
D
2
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