TLC2933_13 Datasheet, PDF (19/24 Pages) Texas Instruments – HIGH-PERFORMANCE PHASE-LOCKED LOOP

TLC2933
HIGHĆPERFORMANCE PHASEĆLOCKED LOOP
REF IN
DGND
VDD
SLAS136B − APRIL 1996 − REVISED JANUARY 2002
APPLICATION INFORMATION
1
LOGIC VDD (Digital)
VCO
14
VCO VDD
AVDD
2 TEST
13
R1†
BIAS
3 _{VCO OUT}
0.22 µF
R3
12
VCO IN
4 FIN −A
11
VCO GND
C2
R2
C1
5 FIN −B
6 ^{PFD OUT}
Phase
Comparator
7
LOGIC GND (Digital)
VCO INHIBIT 10
PFD INHIBIT ₉
8
NC
AGND
Divide
DGND
S1
By
N
S2
† _{RBIAS resistor}
R5
R6
DVDD
Figure 20. Evaluation and Operation Schematic
DGND
PCB layout considerations
The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is
required for evaluation.
The following design recommendations benefit the TLC2933 user:
D External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and
production process.
D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
D LOGIC V_DD and VCO V_DD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
D VCO V_DD to ground and LOGIC V_DD to ground should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
D The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup.
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