OPA2691 Datasheet, PDF (19/30 Pages) Texas Instruments – Dual Wideband, Current-Feedback OPERATIONAL AMPLIFIER

holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply currents in the disable mode are only
those required to operate the circuit of Figure 11. Additional
circuitry ensures that turn-on time occurs faster than turn-off
time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA2691 is operating in a gain of +1,
this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R_F + R_G) will appear as the impedance looking back into the
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R_F + R_G) giving relatively poor input to
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 12
shows these glitches for the circuit of Figure 1 with the input
signal set to 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 12, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the V_DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2kΩ series resistor between the logic gate
and the V_DIS input pin will provide adequate bandlimiting
using just the parasitic input capacitance on the V_DIS pin
while still ensuring adequate logic level swing.
6.0
4.0
2.0
0.0
30
20
10
0
–10
–20
–30
Time (20ns/div)
FIGURE 12. Disable/Enable Glitch.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2691,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C. Operating junction
temperature (T_J) is given by T_A + P_D • θ_JA. The total internal
power dissipation (P_D) is the sum of quiescent power (P_DQ)
and additional power dissipation in the output stage (P_DL) to
deliver load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage across
the part. P_DL will depend on the required output signal and
load but would, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to 1/2
of either supply voltage (for equal bipolar supplies). Under
this condition, P_DL = V_S2/(4 • R_L) where R_L includes feedback
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an
OPA2691 SO-8 in the circuit of Figure 1 operating at the
maximum specified ambient temperature of +85°C with both
outputs driving a grounded 20Ω load to +2.5V.
P_D = 10V • 11.5mA + 2 • [5²/(4 • (20Ω || 804Ω))] = 756mW
Maximum T_J = +85°C + (0.756 • 125°C/W) = 179.5°C
This absolute worst-case condition exceeds specified maxi-
mum junction temperature. Normally this extreme case will
not be encountered. Careful attention to internal power
dissipation is required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency ampli-
fier like the OPA2691 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling capaci-
tor across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PCB.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA2691. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially-
leaded resistors can also provide good high-frequency per-
formance. Again, keep their leads and PCB trace length as
OPA2691
19
SBOS224D
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