MUX36S08 Datasheet, PDF (19/37 Pages) Texas Instruments – Low-Capacitance, Low-Leakage-Current, Precision, Analog Multiplexers

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MUX36S08, MUX36D04
SBOS705A – JANUARY 2016 – REVISED JANUARY 2015
8.8 Charge Injection
The MUX36xxx have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol Q_INJ. Figure 32 shows the setup used to measure charge injection.
VDD
VSS
VDD
VSS
3V
VEN
VOUT
QINJ = CL X V_OUT
VOUT
RS
VS
A0
A1
A2
MUX36S08
S
D
EN
GND
VEN
VOUT
CL
1nF
Figure 32. Charge-Injection Measurement Setup
8.9 Off Isolation
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX36xxx when a 1-V_RMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. Figure 33 shows the setup used to measure, and
the equation used to compute, off isolation.
VDD
0.1µF
VSS
0.1µF
VDD
VSS
NETWORK
ANALYZER
S
50Ÿ
D
GND
50Ÿ
VS
VOUT
RL
50Ÿ
Figure 33. Off Isolation Measurement Setup
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