CP3BT26 Datasheet, PDF (19/375 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

CP3BT26
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SNOSAE5D – FEBRUARY 2007 – REVISED DECEMBER 2013
5 CPU ARCHITECTURE
The CP3BT26 uses the CR16C third-generation 16-bit CompactRISC processor core. The CPU
implements a Reduced Instruction Set Computer (RISC) architecture that allows an effective execution
rate of up to one instruction per clock cycle. For a detailed description of the CPU16C architecture, see
the CompactRISC CR16C Programmer’s Reference Manual which is available on the TI web site
(http://www.ti.com).
The CR16C CPU core includes these internal registers:
• General-purpose registers (R0-R13, RA, and SP)
• Dedicated address registers (PC, ISP, USP, and INTBASE)
• Processor Status Register (PSR)
• Configuration Register (CFG)
The R0-R11, PSR, and CFG registers are 16 bits wide. The R12, R13, RA, SP, ISP and USP registers are
32 bits wide. The PC register is 24 bits wide. Figure 5-1 shows the CPU registers.
Figure 5-1. CPU Registers
Some register bits are designated as “reserved.” Software must write a zero to these bit locations when it
writes to the register. Read operations from reserved bit locations return undefined values.
5.1 GENERAL-PURPOSE REGISTERS
The CompactRISC CPU features 16 general-purpose registers. These registers are used individually as
16-bit operands or as register pairs for operations on addresses greater than 16 bits.
• General-purpose registers are defined as R0 through R13, RA, and SP.
• Registers are grouped into pairs based on the setting of the Short Register bit in the Configuration
Register (CFG.SR). When the CFG.SR bit is set, the grouping of register pairs is upward-compatible
with the architecture of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ... (R11,R10), (R12_L, R11),
(R13_L, R12_L), (R14_L, R13_L) and SP. (R14_L, R13_L) is the same as (RA,ERA).
• When the CFG.SR bit is clear, register pairs are grouped in the manner used by native CR16C
software: (R1,R0), (R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP. R12, R13, RA, and SP are
32-bit registers for holding addresses greater than 16 bits.
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CPU ARCHITECTURE
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