THS7530-Q1 Datasheet, PDF (18/30 Pages) Texas Instruments – THS7530-Q1 High-Speed, Fully Differential, Continuously Variable Gain Amplifier

THS7530-Q1
SLOS932 – DECEMBER 2015
11 Layout
www.ti.com
11.1 Layout Guidelines
The THS7530-Q1 device is available in a thermally-enhanced PowerPAD™ package. Figure 26 shows the
recommended number of vias and thermal land size recommended for best performance. Thermal vias connect
the thermal land to internal or external copper planes and should have a drill diameter sufficiently small so that
the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent
wicking the solder away from the interface between the package body and the thermal land on the surface of the
board during solder reflow. The experiments conducted jointly with Solectron Texas indicate that a via drill
diameter of 0.33 mm (13 mils, or .013 in) or smaller works well when 1-ounce copper is plated at the surface of
the board and simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper
plating is performed, then a solder mask material should be used to cap the vias with a dimension equal to the
via diameter + 0.1 mm minimum. This prevents the solder from being wicked through the thermal via and
potentially creating a solder void in the region between the package bottom and the thermal land on the surface
of the PCB.
TSSOP
14-Pin PWP Package
2´3
3.4
5
Figure 26. Recommended Thermal Land Size and Thermal Via Patterns (Dimensions in mm)
See TI's Technical Brief titled, PowerPAD™ Thermally Enhanced Package (SLMA002) for a detailed discussion
of the PowerPAD™ package, its dimensions, and recommended use.
18
Submit Documentation Feedback
Product Folder Links: THS7530-Q1
Copyright © 2015, Texas Instruments Incorporated