THS7530-Q1 Datasheet, PDF (15/30 Pages) Texas Instruments – THS7530-Q1 High-Speed, Fully Differential, Continuously Variable Gain Amplifier

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9.2 Typical Application
1 kW
1 kW
V_S+ = 5 V
THS7530-Q1
SLOS932 – DECEMBER 2015
0.1 mF
0.1 mF
6.8 mF
24.9 W
0.1 mF
V_IN+
24.9 W
V_CL+
V_CL-
0.1 mF
V_IN-
V_OCM
PD
THS7530
0.1 mF
V_G-
V_S-
V_G+
33 pF
24.9 W
24.9 W
33 pF
0.1 mF
0.1 mF
V_OUT-
V_OUT+
AGC Detect
V_REF
Figure 23. Typical Application Circuit
9.2.1 Design Requirements
A typical application circuit is shown in Figure 23. Two noteworthy aspects of this circuit are the customer’s
automatic gain control (AGC) circuit and the THS7530-Q1 input bias circuit.
The proper design of the AGC circuit is essential for the THS7530-Q1 device to operate properly in the
customer’s application. The method of detecting the amplitude of the differential output of the THS7530-Q1
device and creating the gain-control voltage, V_G+, from the detected amplitude and the reference amplitude, V_ref,
are application-specific and beyond the scope of this document. The bandwidth of the amplitude of the THS7530-
Q1 amplitude control is 15 MHz, which allows for rapid corrections of amplitude errors but which also allows
noise from DC to 15 MHz to create an amplitude error. The trade-off between rapid amplitude correction and
amplitude modulation due to noise is an important design consideration.
The input bias currents of the differential inputs of the THS7530-Q1 device are typically 20 µA. When the
differential inputs are AC-coupled, the bias currents must be supplied as shown in Figure 23. In this circuit, the
DC bias voltage is mid-supply and the AC differential input impedance is 50 Ω. The 0.1-µF capacitor between the
two 24.9-Ω resistors creates an AC ground for the driving circuit.
9.2.2 Detailed Design Procedure
The THS7530-Q1 device is designed for nominal 5-V power supply from V_S+ to V_S–.
The amplifier has fully differential inputs, V_IN+ and V_IN–, and fully differential outputs, V_OUT+ and V_OUT– The inputs
are high impedance and outputs are low impedance. External resistors are recommended for impedance
matching and termination purposes.
The inputs and outputs can be DC-coupled, but for best performance, the input and output common-mode
voltage should be maintained at the midpoint between the two supply pins. The output common-mode voltage is
controlled by the voltage applied to V_OCM. Left unterminated, V_OCM is set to midsupply by internal resistors. A 0.1-
µF bypass capacitor should be placed between V_OCM and ground to reduce common-mode noise. The input
common-mode voltage defaults to midrail when left unconnected. For voltages other than midrail, V_OCMmust be
biased by external means. V_IN+ and V_IN– both require a nominal 30-µA bias current for proper operation.
Therefore, ensure equal input impedance at each input to avoid generating an offset voltage that varies with
gain.
Voltage applied from V_G– to V_G+ controls the gain of the part with 38.8-dB/V gain slope. The input can be
differential or single ended. V_G– must be maintained within –0.6 V and 0.8 V of V_S–for proper operation. The
negative gain input should typically be tied directly to the negative power supply.
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