TMS320C6474_14 Datasheet, PDF (178/215 Pages) Texas Instruments – Multicore Digital Signal Processor

TMS320C6474
SPRS552H – OCTOBER 2008 – REVISED APRIL 2011
www.ti.com
HEX ADDRESS
02D0 0648
02D0 06AC
02D0 06B0
02D0 06B4
02D0 06B8
02D0 06BC
02D0 06C0 - 02D0 06FC
02D0 0700
02D0 0704
02D0 0708
02D0 070C
02D0 0710
02D0 0714
02D0 0718 - 02D0 073C
02D0 0740
02D0 0744
02D0 0748 - 02D0 07DC
02D0 07E0
02D0 07E4
02D0 07E8
02D0 07EC
02D0 07F0 - 02D0 07FC
02D0 0800
02D0 0804
02D0 0808
02D0 080C
02D0 0810
02D0 0814
02D0 0818
02D0 081C
02D0 0820
02D0 0824
02D0 0828
02D0 082C
02D0 0830
02D0 0834
02D0 0838
02D0 083C
02D0 0840
02D0 0844
02D0 0848
02D0 084C
02D0 0850
02D0 0854
02D0 0858
02D0 085C
02D0 08560
Table 7-79. RapidIO Control Registers (continued)
ACRONYM
RIO_Queue10_RxDMA_CP
RIO_Queue11_RxDMA_CP
RIO_Queue12_RxDMA_CP
RIO_Queue13_RxDMA_CP
RIO_Queue14_RxDMA_CP
RIO_Queue15_RxDMA_CP
-
RIO_TXQUEUE_TEAR_DOWN
RIO_TX_CPPI_FLOW_MASKS0
RIO_TX_CPPI_FLOW_MASKS1
RIO_TX_CPPI_FLOW_MASKS2
RIO_TX_CPPI_FLOW_MASKS3
RIO_TX_CPPI_FLOW_MASKS4
-
RIO_RX_QUEUE_TEAR_DOWN
RIO_RX_CPPI_CNTL
-
RIO_TX_QUEUE_CNTL0
RIO_TX_QUEUE_CNTL1
RIO_TX_QUEUE_CNTL2
RIO_TX_QUEUE_CNTL3
-
RXU_MAP_L0
RXU_MAP_H0
RXU_MAP_L1
RXU_MAP_H1
RXU_MAP_L2
RXU_MAP_H2
RXU_MAP_L3
RXU_MAP_H3
RXU_MAP_L4
RXU_MAP_H4
RXU_MAP_L5
RXU_MAP_H5
RXU_MAP_L6
RXU_MAP_H6
RXU_MAP_L7
RXU_MAP_H7
RXU_MAP_L8
RXU_MAP_H8
RXU_MAP_L9
RXU_MAP_H9
RXU_MAP_L10
RXU_MAP_H10
RXU_MAP_L11
RXU_MAP_H11
RXU_MAP_L12
REGISTER NAME
RapidIO Queue10 RX DMA Completion Pointer Register
RapidIO Queue11 RX DMA Completion Pointer Register
RapidIO Queue12 RX DMA Completion Pointer Register
RapidIO Queue13 RX DMA Completion Pointer Register
RapidIO Queue14 RX DMA Completion Pointer Register
RapidIO Queue15 RX DMA Completion Pointer Register
Reserved
RapidIO TX Queue Tear Down Register
RapidIO TX CPPI Support Flow Masks 0 Register
RapidIO TX CPPI Support Flow Masks 1 Register
RapidIO TX CPPI Support Flow Masks 2 Register
RapidIO TX CPPI Support Flow Masks 3 Register
RapidIO TX CPPI Support Flow Masks 4 Register
Reserved
RapidIO RX Queue Tear Down Register
RapidIO CPPI Control Register
Reserved
RapidIO TX Queue Control 0 Register
RapidIO TX Queue Control 1 Register
RapidIO TX Queue Control 2 Register
RapidIO TX Queue Control 3 Register
Reserved
Mailbox-to-Queue Mapping Register L0
Mailbox-to-Queue Mapping Register H0
Mailbox-to-Queue Mapping Register L1
Mailbox-to-Queue Mapping Register H1
Mailbox-to-Queue Mapping Register L2
Mailbox-to-Queue Mapping Register H2
Mailbox-to-Queue Mapping Register L3
Mailbox-to-Queue Mapping Register H3
Mailbox-to-Queue Mapping Register L4
Mailbox-to-Queue Mapping Register H4
Mailbox-to-Queue Mapping Register L5
Mailbox-to-Queue Mapping Register H5
Mailbox-to-Queue Mapping Register L6
Mailbox-to-Queue Mapping Register H6
Mailbox-to-Queue Mapping Register L7
Mailbox-to-Queue Mapping Register H7
Mailbox-to-Queue Mapping Register L8
Mailbox-to-Queue Mapping Register H8
Mailbox-to-Queue Mapping Register L9
Mailbox-to-Queue Mapping Register H9
Mailbox-to-Queue Mapping Register L10
Mailbox-to-Queue Mapping Register H10
Mailbox-to-Queue Mapping Register L11
Mailbox-to-Queue Mapping Register H11
Mailbox-to-Queue Mapping Register L12
178 Peripheral Information and Electrical Specifications
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