TMS320C6474_14 Datasheet, PDF (139/215 Pages) Texas Instruments – Multicore Digital Signal Processor

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TMS320C6474
SPRS552H – OCTOBER 2008 – REVISED APRIL 2011
Table 7-41. Switching Characteristics for I2C Timings ⁽¹⁾
(see Figure 7-26)
NO.
STANDARD MODE
FAST MODE
MIN
MAX
MIN
MAX
16
t_c(SCL)
Cycle time, SCL
10
2.5
17
t_d(SCLH-SDAL)
Delay time, SCL high to SDA low (for a
4.7
0.6
repeated START condition)
18
t_d(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START
4
0.6
and a repeated START condition)
19
t_w(SCLL)
Pulse duration, SCL low
4.7
20
t_w(SCLH)
Pulse duration, SCL high
4
21
t_d(SDAV-SDLH)
Delay time, SDA valid to SCL high
250
22
t_{tw(SDLL-SDAV)}
Valid time, SDA valid after SCL low (for PC
0
bus devices)
1.3
0.6
100
0
0.9
23
T_w(SDAH)
24
t_r(SDA)
25
t_r(SDL)
26
t_f(SDA)
27
t_f(SCL)
28
t_d(SCLH-SDAH)
Pulse duration, SDA high between STOP and
START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high (for STOP
condition)
4.7
1.3
1000 20 + 0.1C_b ⁽¹⁾
300
1000 20 + 0.1C_b ⁽¹⁾
300
300 20 + 0.1C_b ⁽¹⁾
300
300 20 + 0.1C_b ⁽¹⁾
300
4
0.6
29 C_p
Capacitance for each I2C pin
10
10
(1) C_b = total capacitance of one bus line, in pF. If mixed with HS-mode devices, faster fall-times are allowed.
UNIT
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
ns
μs
pF
Figure 7-26. I2C Transmit Timings
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Peripheral Information and Electrical Specifications 139
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