TMS320C6474_14 Datasheet, PDF (168/215 Pages) Texas Instruments – Multicore Digital Signal Processor

TMS320C6474
SPRS552H – OCTOBER 2008 – REVISED APRIL 2011
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7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)
7.16.1 VCP2 Device-Specific Information
The C6474 device has a high-performance embedded coprocessor Viterbi-Decoder Coprocessor (VCP2)
that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock
divided-by-3 can decode over 694 7.95-Kbps adaptive multi-rate (AMR)(K = 9, R = 1/3) voice channels.
The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and
flexible polynomials, while generating hard decisions or soft decisions. Communications between the
VCP2 and the CPU are carried out through the EDMA3 controller.
The VCP2 supports:
• Unlimited frame sizes
• Code rates 3/4, 1/2, 1/3, 1/4, and 1/5
• Constraint lengths 5, 6, 7, 8, and 9
• Programmable encoder polynomials
• Programmable reliability and convergence lengths
• Hard and soft decoded decisions
• Tail and convergent modes
• Yamamoto logic
• Tail biting logic
• Various input and output FIFO lengths
For more detailed information on the VCP2, see the TMS320C6474 DSP Viterbi-Decoder Coprocessor 2
(VCP2) Reference Guide (literature number SPRUG20).
168 Peripheral Information and Electrical Specifications
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