NSBMC096 Datasheet, PDF (17/20 Pages) Texas Instruments – NSBMC096 Burst Memory Controller

Errata for NSBMC096
The document defines all known errata related to the opera-
tion of the NSBMC096 Memory Controller
ERRATUM 1
Pulse mode interrupts from the NSBMC096 are two cycles
long The current rev of the i960CA CF requires a minimum
interrupt pulse width of three clock cycles
RECOMMENDED FIX
Program the NSBMC096 for level mode interrupts
ERRATUM 2
When the NSBMC096 is programmed for extended timing
mode operation back to back memory read cycles will fail
RECOMMENDED FIX
Program the i960CA CF memory region for the NSBMC096
to insert one wait state following each memory access (i e
Set N_XDA e 1)
Ordering Code Information
NS BMC 096 VF 33
National Semiconductor
Frequency
Mode
Burst Mode Controller
Processor
Obsolete ^Inteli960
16 MHz
25 MHz
33 MHz
Packaging
VF 132-Lead PQFP
16