NSBMC096 Datasheet, PDF (12/20 Pages) Texas Instruments – NSBMC096 Burst Memory Controller

Timing Parameters
INTERFACE TIMING
The NSBMC096 interface to the i960 CA CF has been de-
signed for direct interconnect It is not necessary to place
other Iogic devices between the processor and the
NSBMC096 nor is their use encouraged The introduction
of intermediate address or control signal buffers can result
in skews or delays that will require the system clock fre-
quency to be derated for operation under worst case condi-
tions The timing diagrams presented in this section assume
that all signals between the processor and the NSBMC096
are un-buffered
REFRESH TIMING
depending on whether Cycle Extend is enabled If multiple
access cycles are requested back to back then the BMC will
pause for a minimum of 2 clocks between RAS cycles to
insure that the RAS pre-charge time is met This will result in
5 or 6 clocks between successive simple cycles
Figure 6 shows the timing relationship between the system
clock processor control signals and NSBMC096 outputs
AIl NSBMC096 outputs are derived synchronously with the
exception of t_ARA (processor address to row address de-
lay) Two simple access cycles are shown in the diagram
The first is a read cycle that assumes that the NSBMC096
was idle prior to the start of the cycle the second is backed
onto the first to show the effect of RAS pre-charge imposed
Figure 5 details the timing of the RAS only refresh per-
by NSBMC096 If Cycle Extend is enabled a wait state will
formed by the memory controller when there is a competing
be inserted after cycles T3 and T8
request from a bus master A competing request is defined
as any request that occurs between T0 and T5 For any
request in this range the timing is exactly as shown As
illustrated the diagram represents the timing that results
when Cycle Extend is disabled If Cycle Extend is enabled
an additional cycle is inserted at T3 and T8
SIMPLE ACCESS TIMING
The NSBMC096 can return data to the processor in only 3
te ^{or 4 clock cycles for a basic access (2 or 3 wait states)}
BURST ACCESS TIMING
When a burst access is requested by the processor the
NSBMC096 generates the sequence in Figure 7 If the burst
is for 2 words (load double for example) the processor gen-
erates BLAST in T5 and the sequence is shortened appro-
priately The first access of the burst sequence begins in the
same manner as a simple access Consequently the timing
parameters from Figure 6 may be applied in Figure 7
Obsole ^{FIGURE5 RefreshTiming}
TL V 11805 – 8
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