NSBMC096 Datasheet, PDF (14/20 Pages) Texas Instruments – NSBMC096 Burst Memory Controller

Timing Parameters (Continued)
te _{FIGURE 8 Burst Access w t PCache Hit}
TL V 11805 – 11
le ^{Figures 8 and 9 show the sequence of events that can oc-}
cur when PCache is enabled The sequence in Figure 8
shows two back-to-back bursts in the same page This type
Obso ^{of sequence yields the highest data transfer rate achievable}
with DRAM Figure 9 shows the worst case scenario This
example shows two back-to-back simple access to different
rows with PCache is enabled
FIGURE 9 Simple Access w t PCache Miss
13
TL V 11805 – 12