THS4021_16 Datasheet, PDF (15/29 Pages) Texas Instruments – 350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS

THS4021
THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
General Thermal Pad Design Considerations
The THS402x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 37(a) and Figure 37(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 37(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a design breakthrough, combining the small area and ease of the surface
mount assembly method to eliminate the previously difficult mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
M0031-01
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 37. Views of Thermally Enhanced DGN Package
Although there are many ways to heatsink this device properly, the following steps illustrate the recommended
approach.
Thermal pad area = 68 mils ´ 70 mils (1.73 mm ´1.78 mm) with 5 vias.
Via diameter = 13 mils (0.33 mm).
Figure 38. Thermal Pad PCB Etch and Via Pattern
M0032-02
1. Prepare the PCB with a top side etch pattern as shown in Figure 38. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0.33 mm) in diameter. Keep
them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the THS402xDGN IC. These additional vias may be larger than the
13-mil (0.33-mm) diameter vias directly under the thermal pad. They can be larger because they are not in
the thermal pad area to be soldered, so wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS402xDGN package should connect to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
Copyright © 1999–2007, Texas Instruments Incorporated
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