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TCA9545A Datasheet, PDF (15/30 Pages) Texas Instruments – Low Voltage 4-channel I2C and SMbus Switch With Interrupt Logic and Reset Functions
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TCA9545A
SCPS204B – JANUARY 2014 – REVISED MARCH 2014
9.6 Control Register
9.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9545A is shown in Figure 14. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address terminals, and they must be pulled high or low.
Slave Address
1 1 1 0 0 A1 A0 R/W
Fixed
Hardware
Selectable
Figure 14. TCA9545A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
9.6.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9545A,
which is stored in the control register (see Figure 15). If multiple bytes are received by the TCA9545A, it saves
the last byte received. This register can be written and read via the I2C bus.
Interrupt Bits
(Read Only)
Channel-Selection Bits
(Read/Write)
76 5 432 1 0
INT3 INT2 INT1 INT0 B3 B2 B1 B0
Figure 15. Control Register
Channel 0
Channel 1
Channel 2
Channel 3
INT0
INT1
INT2
INT3
9.6.3 Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). After the TCA9545A has been addressed, the control register is written. The four LSBs of the control
byte are used to determine which channel or channels are to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition must occur always right after the acknowledge cycle.
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