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SN74AVCH16T245_15 Datasheet, PDF (15/30 Pages) Texas Instruments – 16-Bit Dual-Supply Bus Transceiver
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9 Detailed Description
SN74AVCH16T245
SCES587D – AUGUST 2004 – REVISED NOVEMBER 2015
9.1 Overview
The SN74AVCH16T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and
control pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port can accept I/O
voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on DIR
allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to
low. When OE is set to high, both A and B are in the high-impedance state.
SN74AVCH16T245 features Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use
of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using off output current ( Ioff).
The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state.
9.2 Functional Block Diagram
1
1DIR
47
1A1
48
1OE
2
1B1
24
2DIR
36
2A1
25
2OE
13
2B1
To Seven Other Channels
To Seven Other Channels
9.3 Feature Description
9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V
Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V making the device suitable for translating
between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V).
9.3.2 Partial-Power-Down Mode Operation
The Ioff circuitry will prevent backflow current by disabling I/O output circuits when device is in partial power-down
mode. This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
9.3.3 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance
state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to either bus.
Copyright © 2004–2015, Texas Instruments Incorporated
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