DS50PCI402 Datasheet, PDF (15/36 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

Symbol
DE-EMPHASIS
DJD1
DJD2
DJD3
DJD4
Parameter
Conditions
Min
Residual Deterministic 28” of 5 mil stripline FR4,
Jitter at 5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,1; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F.
(Note 3, Note 11)
Residual Deterministic 28” of 5 mil microstrip FR4,
Jitter at 2.5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,0; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F.
(Note 3, Note 11)
Residual Deterministic 7 meters of 24 AWG PCIe cable,
Jitter at 5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,1; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F.
(Note 3, Note 11)
Residual Deterministic 7 meters of 24 AWG PCIe cable,
Jitter at 2.5 Gbps
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,0; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F.
(Note 3, Note 11)
Typ
Max
Units
0.02
0.09
UI_P-P
0.03
0.05
UI_P-P
0.03
0.13
UI_P-P
0.04
0.06
UI_P-P
Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 3: Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 5: Allowed supply noise (mV_P-P sine wave) under typical conditions.
Note 6: Input Return Loss also uses the setup shown in Figure 6. The blocking / biasing circuit is replaced with a simple AC coupling capacitor for each input to
emulate a typical PCIe application.
Note 7: PCIe 2.0 transmit jitter specifications - actual device jitter is much less. Actual device Rj and Dj has been characterized and specified with test loads
outlined in the EQUALIZATION and DE-EMPHASIS sections of the Electrical Characteristics table.
Note 8: Guaranteed by device characterization
Note 9: Propagation Delay measurements for Part to Part skew are all based on devices operating under indentical temperature and supply voltage conditions.
Note 10: Propagation Delay measurements will change slightly based on the level of EQ selected. EQ Bypass will result in the shortest propagation delays.
Note 11: Residual DJ measurements subtract out deterministic jitter present at the generator outputs. For 2.5 Gbps generator Dj = 0.0275 UI and for 5.0 Gbps
generator Dj = 0.035 UI.
Note 12: Measured with a repeating K28.5 pattern at a data rate of 2.5 Gbps and 5.0 Gbps.
Note 13: Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table.
Note 14: Measured at default SD_TH settings
Note 15: Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%.
Note 16: Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to GND overrides
this default setting.
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