DS50PCI402 Datasheet, PDF (14/36 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

Symbol
V_{TX-CM-DC- LINE-DELTA}
T_{TX-IDLE-SET-TO -IDLE}
T_{TX-IDLE-TO -DIFF-DATA}
T_PDEQ
T_PD
T_LSK
T_PPSK
EQUALIZATION
DJE1
DJE2
DJE3
DJE4
RJ
Parameter
Conditions
Min
Absolute Delta of DC
Common Mode
Voltage between Tx+
and Tx-
Max time to transition to VIN = 800 mVp-p, 5 Gbps,
valid diff signaling after Figure 5
leaving Electrical Idle
Max time to transition to VIN = 800 mVp-p, 5 Gbps,
valid diff signaling after Figure 5
leaving Electrical Idle
Differential
EQ = 11,
Propagation Delay
+4.0 dB @ 2.5 GHz , Figure 4
150
(Note 10)
Differential
EQ = FF,
Propagation Delay
Equalizer Bypass, Figure 4
120
(Note 10, Note 9)
Lane to Lane Skew in a T_A = 25C,V_DD = 2.5V
Single Part
(Note 8, Note 9)
Part to Part
Propagation Delay
Skew
T_A = 25C,V_DD = 2.5V
Residual Deterministic
Jitter at 5 Gbps
42” of 5 mil stripline FR4,
EQ1,0=F,1; K28.5 pattern,
DEMx=0, Tx Launch Amplitude
1.0 Vp-p, SD_TH=F. (Note 3,
Note 11)
Residual Deterministic
Jitter at 2.5 Gbps
42” of 5 mil stripline FR4,
EQ1,0=F,1; K28.5 pattern,
DEMx=0, Tx Launch Amplitude
1.0 Vp-p, SD_TH=F. (Note 3,
Note 11)
Residual Deterministic
Jitter at 5 Gbps
7 meters of 24 AWG PCIe cable,
EQ1,0=1,0; K28.5 pattern,
DEMx=0, Tx Launch Amplitude
1.0 Vp-p, SD_TH=F. (Note 3,
Note 11)
Residual Deterministic
Jitter at 2.5 Gbps
7 meters of 24 AWG PCIe cable,
EQ1,0=1,0; K28.5 pattern,
DEMx=0, Tx Launch Amplitude
1.0 Vp-p, SD_TH=F. (Note 3,
Note 11)
Random Jitter
Tx Launch Amplitude 1.0 Vp-p,
SD_TH=F, Repeating 1100b
(D24.3) pattern. (Note 3)
Typ
Max
25
Units
mV
6.5
9.5
nS
5.5
8
nS
200
250
ps
170
220
ps
27
ps
35
ps
0.02
0.09
UI_P-P
0.02
0.04
UI_P-P
0.02
0.11
UI_P-P
0.03
0.07
UI_P-P
<0.5
psrms
13
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