DS50PCI402 Datasheet, PDF (11/36 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

Manual Control Of RXDETA/B In A
PCIe Environment
In some cases manual control of RXDETA/B may be desir-
able. In order for upstream and downstream PCIe subsys-
tems to communicate in a cabling environment, the PCIe
specification includes several auxiliary or sideband signals to
manage system-level functionality or implementation. Similar
methods are used in backplane applications, but the exact
implementation falls outside the PCIe standard. Initial com-
munication from the downstream subsystem to the upstream
subsystem is done with the CPRSNT# auxiliary signal. The
CPRSNT# signal is asserted Low by the downstream com-
ponentry after the "Power Good" condition has been estab-
lished. This mechanism allows for the upstream subsystem
to determine whether the power is good within the down-
stream subsystem, enable the reference clock, and initiate
the Link Training Sequence.
FIGURE 2. Typical PCIe System Timing
30107312
The signals shown in the graphic could be easily replicated
within the downstream subsystem and used to externally con-
trol the common mode input termination impedance on the
DS50PCI402. Often an onboard microcontroller will be used
to handle events like power-up, power-down, power saving
modes, and hot insertion. The microcontroller would use the
same information to determine when to enable and disable
the DS50PCI402 input termination. In applications that re-
quire SMBus control, the microcontroller could also delay any
response to the upstream subsystem to allow sufficient time
to correctly program the DS50PCI402 and other devices on
the board.
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