LP38690-ADJ_16 Datasheet, PDF (14/27 Pages) Texas Instruments – 1-A Low Dropout CMOS Linear Regulator

LP38690-ADJ, LP38692-ADJ
SNVS323I – DECEMBER 2004 – REVISED FEBRUARY 2016
8.2 Typical Application
V_IN
IN
OUT
LP38690
-ADJ
GND ^ADJ
R2
V_OUT
R1
www.ti.com
Figure 29. LP38690-ADJ Typical Application
V_IN
V_OUT
IN
OUT
LP38692
V_EN
EN _-ADJ
ADJ
R1
GND
R2
V_OUT = V_ADJ × (1 + R1/R2)
Figure 30. LP38692-ADJ Typical Application
8.2.1 Design Requirements
For typical CMOS voltage regulator applications, use the parameters listed in Table 1
Table 1. Design Parameters
DESIGN PARAMETER
Minimum input voltage
Minimum output voltage
Output current
Input and output capacitors
Input/output capacitor ESR range
EXAMPLE VALUE
2.7 V
1.25 V
150 mA
1 µF
0 mΩ to 100 mΩ
8.2.2 Detailed Design Procedure
8.2.2.1 Setting The Output Voltage
The output voltage is set using the external resistors R1 and R2 (see Figure 29 and Figure 30). The output
voltage is given by Equation 1:
V_OUT = V_ADJ × (1 + ( R1 / R2 ) )
(1)
Because the part has a minimum load current requirement of 100 µA, TI recommends that R2 always be 12 kΩ
or less to provide adequate loading. Even if a minimum load is always provided by other means, it is not
recommended that very high value resistors be used for R1 and R2 because it can make the ADJ node
susceptible to noise pickup. A maximum value of 100 kΩ is recommended for R2 to prevent this from occurring.
8.2.2.2 External Capacitors
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
8.2.2.2.1 Input Capacitor
An input capacitor of at least 1 µF is required (ceramic recommended). The capacitor must be located not more
than one centimeter from the IN pin and returned to a clean analog ground.
14
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LP38690-ADJ LP38692-ADJ