LP38690-ADJ_16 Datasheet, PDF (13/27 Pages) Texas Instruments – 1-A Low Dropout CMOS Linear Regulator

www.ti.com
8 Application and Implementation
LP38690-ADJ, LP38692-ADJ
SNVS323I – DECEMBER 2004 – REVISED FEBRUARY 2016
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Reverse Voltage
A reverse voltage condition exists when the voltage at the OUT pin is higher than the voltage at the IN pin.
Typically this happens when IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that the
input-to-output voltage becomes reversed. A less-common condition is when an alternate voltage source is
connected to the output.
There are two possible paths for current to flow from the OUT pin back to the input during a reverse voltage
condition.
1. While V_IN is high enough to keep the control circuity alive, and the EN pin (LP38692-ADJ only) is above the
V_EN(ON) threshold, the control circuitry will attempt to regulate the output voltage. If the input voltage is less
than the programmed output voltage, the control circuit drives the gate of the pass element to the full ON
condition. In this condition, reverse current flows from the OUT pin to the IN pin, limited only by the R_DS(ON) of
the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF
in this manner does not damage the device as the current rapidly decays. However, continuous reverse
current must be avoided. When the EN pin is low this condition is prevented.
2. The internal PFET pass element has an inherent parasitic diode. During normal operation, the input voltage
is higher than the output voltage and the parasitic diode is reverse biased. However, when V_IN is below the
value where the control circuity is alive, or the EN pin is low (LP38692-ADJ only), and the output voltage is
more than 500 mV (typical) above the input voltage the parasitic diode becomes forward biased and current
flows from the OUT pin to the IN pin through the diode. The current in the parasitic diode must be limited to
less than 1-A continuous and 5-A peak.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the OUT pin
must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is recommended for
this protective clamp.
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LP38690-ADJ LP38692-ADJ