LM3S9U92_15 Datasheet, PDF (14/1412 Pages) Texas Instruments – Stellaris LM3S9U92 Microcontroller

Table of Contents
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 763
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 764
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 765
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 765
Figure 15-1. I²C Block Diagram ............................................................................................. 797
Figure 15-2. I²C Bus Configuration ........................................................................................ 798
Figure 15-3. START and STOP Conditions ............................................................................. 799
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 799
Figure 15-5. R/S Bit in First Byte ............................................................................................ 800
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 800
Figure 15-7. Master Single TRANSMIT .................................................................................. 804
Figure 15-8. Master Single RECEIVE ..................................................................................... 805
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 806
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 807
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 808
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 809
Figure 15-13. Slave Command Sequence ................................................................................ 810
Figure 16-1. I²S Block Diagram ............................................................................................. 835
Figure 16-2. I²S Data Transfer ............................................................................................... 838
Figure 16-3. Left-Justified Data Transfer ................................................................................ 838
Figure 16-4. Right-Justified Data Transfer .............................................................................. 838
Figure 17-1. CAN Controller Block Diagram ............................................................................ 872
Figure 17-2. CAN Data/Remote Frame .................................................................................. 874
Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 882
Figure 17-4. CAN Bit Time .................................................................................................... 886
Figure 18-1. Ethernet Controller ............................................................................................. 923
Figure 18-2. Ethernet Controller Block Diagram ...................................................................... 923
Figure 18-3. Ethernet Frame ................................................................................................. 925
Figure 18-4. Interface to an Ethernet Jack .............................................................................. 933
Figure 19-1. USB Module Block Diagram ............................................................................... 984
Figure 20-1. Analog Comparator Module Block Diagram ....................................................... 1123
Figure 20-2. Structure of Comparator Unit ............................................................................ 1125
Figure 20-3. Comparator Internal Reference Structure .......................................................... 1125
Figure 21-1. PWM Module Diagram ..................................................................................... 1138
Figure 21-2. PWM Generator Block Diagram ........................................................................ 1138
Figure 21-3. PWM Count-Down Mode .................................................................................. 1142
Figure 21-4. PWM Count-Up/Down Mode ............................................................................. 1142
Figure 21-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1143
Figure 21-6. PWM Dead-Band Generator ............................................................................. 1144
Figure 22-1. QEI Block Diagram .......................................................................................... 1214
Figure 22-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1216
Figure 23-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1236
Figure 23-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1237
Figure 26-1. Load Conditions ............................................................................................... 1318
Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1319
Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1319
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July 03, 2014
Texas Instruments-Production Data